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Message-ID: <718082aebcc3ab4d9169a4abbe968ec1@kernel.org>
Date: Sun, 29 Dec 2019 11:29:16 +0000
From: Marc Zyngier <maz@...nel.org>
To: James Tai <james.tai@...ltek.com>
Cc: linux-realtek-soc@...ts.infradead.org, mark.rutland@....com,
devicetree@...r.kernel.org,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
linux-kernel@...r.kernel.org, robh+dt@...nel.org,
Robin Murphy <robin.murphy@....com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 2/2] arm64: dts: realtek: Add RTD1319 SoC and Realtek
PymParticle EVB
On 2019-12-29 07:46, James Tai wrote:
> Hi Marc,
>
> Thanks for review.
>
>> > + timer {
>> > + compatible = "arm,armv8-timer";
>> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>>
>> Nit: At some point, it'd be good to be able to describe the EL2
>> virtual timer
>> interrupt too. Not specially important, but since these ARMv8.2 CPUs
>> have it...
>
> I will add the EL2 virtual timer interrupt to timer node.
If you do this, please update the binding first, as this interrupt
is not described there yet.
>
>> > + gic: interrupt-controller@...00000 {
>> > + compatible = "arm,gic-v3";
>> > + reg = <0xff100000 0x10000>,
>> > + <0xff140000 0xc0000>;
>>
>> Are you sure about the size of the GICR region? For 4 CPUs, it should
>> be
>> 0x80000. Here, you have a range for 6 CPUs.
>
> The GICR region should be 0x80000 because the RTD1319 SoC have only 4
> CPUs.
OK. Please verify that this is actually the case, and that the last
redistributor (at offset 0x60000) has GICR_TYPER.Last set. I have
recently seen GICs configured for a larger number of CPUs where
some of them were disabled in HW, and the DT was wrongly describing
some of the redistributors only, leading to SW crashes.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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