linux-kernel - Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges

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Date:   Thu, 2 Jan 2020 15:55:53 -0700
From:   Rob Herring <robh@...nel.org>
To:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc:     Bjorn Helgaas <bhelgaas@...gle.com>,
        Mark Rutland <mark.rutland@....com>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        Marek Vasut <marek.vasut+renesas@...il.com>,
        Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
        PCI <linux-pci@...r.kernel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Arnd Bergmann <arnd@...db.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Andrew Murray <andrew.murray@....com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        "open list:MEDIA DRIVERS FOR RENESAS - FCP" 
        <linux-renesas-soc@...r.kernel.org>,
        Chris Paterson <Chris.Paterson2@...esas.com>,
        Frank Rowand <frowand.list@...il.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Simon Horman <horms@...ge.net.au>,
        Shawn Lin <shawn.lin@...k-chips.com>,
        Tom Joseph <tjoseph@...ence.com>,
        Heiko Stuebner <heiko@...ech.de>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [v2 3/6] of: address: add support to parse PCI outbound-ranges

On Thu, Jan 2, 2020 at 1:44 AM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
>
> Hi Rob,
>
> On Thu, Dec 19, 2019 at 11:31 PM Rob Herring <robh@...nel.org> wrote:
> >
> > On Mon, Dec 16, 2019 at 08:49:23AM +0000, Lad, Prabhakar wrote:
> > > Hi Rob,
> > >
> > > Thank you for the review.
> > >
> > > On Fri, Dec 13, 2019 at 8:37 PM Rob Herring <robh+dt@...nel.org> wrote:
> > > >
> > > > On Fri, Dec 13, 2019 at 2:48 AM Lad Prabhakar
> > > > <prabhakar.csengg@...il.com> wrote:
> > > > >
> > > > > From: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@...renesas.com>
> > > > >
> > > > > this patch adds support to parse PCI outbound-ranges, the
> > > > > outbound-regions are similar to pci ranges except it doesn't
> > > > > have pci address, below is the format for bar-ranges:
> > > > >
> > > > > outbound-ranges = <flags upper32_cpuaddr lower32_cpuaddr
> > > > >                    upper32_size lower32_size>;
> > > >
> > > > You can't just make up a new ranges property. Especially one that
> > > > doesn't follow how 'ranges' works. We already have 'dma-ranges' to
> > > > translate device to memory addresses.
> > > >
> > > > Explain the problem or feature you need, not the solution you came up
> > > > with. Why do you need this and other endpoint bindings haven't?
> > > >
> > > rcar SoC's supports multiple outbound region for mapping the PCI address
> > > locally to the system. This lead to discussion where there exist controllers
> > > which support regions for high/low priority transfer and similarly regions
> > > for large/small memory allocations, as a result a new ranges property was
> > > added, where we can specify the flags which would indicate how the outbound
> > > region can be used during requests.
> >
> > What are the flags?
>
> below are the flags which were discussed in first version of the
> series, but since the driver is
> currently using just PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC flag I'll be
> dropping them in
> next version (suggested by Kishon) and rest will be added as and when
> required by the driver.
>
>  * @PCI_EPC_WINDOW_FLAG_MULTI_ALLOC: Indicates multiple chunks of memory can be
>  *                                  allocated from same window
>  * @PCI_EPC_WINDOW_FLAG_NON_MULTI_ALLOC: Indicates only single memory allocation
>  *                                      is possible on the window
>  * @PCI_EPC_WINDOW_FLAG_LARGE_ALLOC: Window is used for large memory allocation
>  * @PCI_EPC_WINDOW_FLAG_SMALL_ALLOC: Window is used for small memory allocation
>  * @PCI_EPC_WINDOW_FLAG_HIGH_PRI_ALLOC: Window is used for high priority data
>  *                                     transfers
>  * @PCI_EPC_WINDOW_FLAG_LOW_PRI_ALLOC: Window is used for low priority data
>  *                                    transfers

Looks like configuration or policy, not something that belongs in DT.
Coupling driver features and DT changes is not good for ABI compatible
changes either.

I'm hesitant to accept any PCI endpoint binding additions because they
don't seem to be completely thought out in terms of supporting
different usecases.

Rob