linux-kernel - Re: [PATCH 1/3] arm64: dts: sc7180: Add Venus video codec DT node

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Message-ID: <17bc9ed78316f483fea273849d39d6a8@codeaurora.org>
Date:   Thu, 02 Jan 2020 13:24:08 +0530
From:   vgarodia@...eaurora.org
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     Dikshita Agarwal <dikshita@...eaurora.org>,
        linux-media@...r.kernel.org, stanimir.varbanov@...aro.org,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] arm64: dts: sc7180: Add Venus video codec DT node

Hi Bjorn,

Thanks for your review comments.

On 2019-12-29 08:48, Bjorn Andersson wrote:
> On Thu 19 Dec 23:59 PST 2019, Dikshita Agarwal wrote:
> 
>> This adds Venus video codec DT node for sc7180.
>> 
>> Signed-off-by: Dikshita Agarwal <dikshita@...eaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 36 
>> ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 36 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index 6876aae2..42c70f5 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -10,6 +10,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/phy/phy-qcom-qusb2.h>
>>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +#include <dt-bindings/clock/qcom,videocc-sc7180.h>
>> 
>>  / {
>>  	interrupt-parent = <&intc>;
>> @@ -66,6 +67,11 @@
>>  			compatible = "qcom,cmd-db";
>>  			no-map;
>>  		};
>> +
>> +		venus_mem: memory@...00000 {
>> +			reg = <0 0x8F600000 0 0x500000>;
>> +			no-map;
>> +		};
>>  	};
>> 
>>  	cpus {
>> @@ -1042,6 +1048,36 @@
>>  			};
>>  		};
>> 
>> +		venus: video-codec@...0000 {
>> +			compatible = "qcom,sc7180-venus";
>> +			reg = <0 0x0aa00000 0 0xff000>;
>> +			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
>> +			power-domains = <&videocc VENUS_GDSC>,
> 
> Should this be aligned with the DT refactoring done for sdm845, where
> the GDSC is moved into the *-core subnodes etc?
This is already aligned to new refactored design i.e clocks/GDSCs are no 
more
core specific.

> Regards,
> Bjorn
> 
>> +					<&videocc VCODEC0_GDSC>;
>> +			power-domain-names = "venus", "vcodec0";
>> +			clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
>> +				<&videocc VIDEO_CC_VENUS_AHB_CLK>,
>> +				<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
>> +				<&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
>> +				<&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
>> +			clock-names = "core", "iface", "bus",
>> +					"vcodec0_core", "vcodec0_bus";
>> +			iommus = <&apps_smmu 0x0C00 0x60>;
>> +			memory-region = <&venus_mem>;
>> +
>> +			video-core0 {
>> +					compatible = "venus-decoder";
>> +			};
>> +
>> +			video-core1 {
>> +					compatible = "venus-encoder";
>> +			};
>> +
>> +			video-firmware {
>> +					iommus = <&apps_smmu 0x0C42 0x0>;
>> +			};
>> +		};
>> +
>>  		pdc: interrupt-controller@...0000 {
>>  			compatible = "qcom,sc7180-pdc", "qcom,pdc";
>>  			reg = <0 0x0b220000 0 0x30000>;
>> --
>> 1.9.1
>>