lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Fri, 3 Jan 2020 11:54:51 +0800
From:   Dilip Kota <eswara.kota@...ux.intel.com>
To:     Philipp Zabel <p.zabel@...gutronix.de>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Cc:     robh@...nel.org, martin.blumenstingl@...glemail.com,
        cheol.yong.kim@...el.com, chuanhua.lei@...ux.intel.com,
        qi-ming.wu@...el.com
Subject: Re: [PATCH v5 2/2] reset: intel: Add system reset controller driver


On 1/2/2020 7:43 PM, Philipp Zabel wrote:
> On Mon, 2019-12-16 at 14:55 +0800, Dilip Kota wrote:
>> Add driver for the reset controller present on Intel
>> Gateway SoCs for performing reset management of the
>> devices present on the SoC. Driver also registers a
>> reset handler to peform the entire device reset.
>>
>> Signed-off-by: Dilip Kota <eswara.kota@...ux.intel.com>
>> ---
>> Changes on v5:
>> 	Rebase patches on v5.5-rc1 kernel
>>
>> Changes on v4:
>> 	No Change
>>
>> Changes on v3:
>> 	Address review comments:
>> 		Remove intel_reset_device() as not supported
>> 	reset-intel-syscon.c renamed to reset-intel-gw.c
>> 	Remove syscon and add regmap logic
>> 	Add support to legacy xrx200 SoC
>> 	Use bitfield helper functions for bit operations.
>> 	Change config RESET_INTEL_SYSCON-> RESET_INTEL_GW
>>   drivers/reset/Kconfig          |   9 ++
>>   drivers/reset/Makefile         |   1 +
>>   drivers/reset/reset-intel-gw.c | 262 +++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 272 insertions(+)
>>   create mode 100644 drivers/reset/reset-intel-gw.c
[...]
>> +					set == !!(val & BIT(stat_bit)),
>> +					20, timeout);
>> +}
>> +
>> +static int intel_assert_device(struct reset_controller_dev *rcdev,
>> +			       unsigned long id)
>> +{
>> +	struct intel_reset_data *data = to_reset_data(rcdev);
>> +	int ret;
>> +
>> +	ret = intel_set_clr_bits(data, id, true, 200);
> timeout doesn't have to be a parameter to intel_set_clr_bits.
Agree, not required to be a parameter.
Will update in the next patch version.
>
> [...]
>> +struct intel_reset_soc xrx200_data = {
>> +	.legacy =		true,
>> +	.reset_cell_count =	3,
>> +};
>> +
>> +struct intel_reset_soc lgm_data = {
>> +	.legacy =		false,
>> +	.reset_cell_count =	2,
>> +};
> Please make these two static const, otherwise this looks fine to me.
My miss, could have taken care.

I will update them in the next patch version.

Thanks Philipp for your time in reviewing the patch and giving the inputs.

Regards,
Dilip

>
> regards
> Philipp
>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ