linux-kernel - [PATCH v2 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled

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Message-Id: <1578024801-39039-1-git-send-email-yash.shah@sifive.com>
Date:   Fri,  3 Jan 2020 09:43:19 +0530
From:   Yash Shah <yash.shah@...ive.com>
To:     robh+dt@...nel.org, mark.rutland@....com, paul.walmsley@...ive.com,
        palmer@...belt.com
Cc:     aou@...s.berkeley.edu, bmeng.cn@...il.com, green.wan@...ive.com,
        allison@...utok.net, alexios.zavras@...el.com,
        gregkh@...uxfoundation.org, tglx@...utronix.de, bp@...e.de,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, sachin.ghadi@...ive.com,
        Yash Shah <yash.shah@...ive.com>
Subject: [PATCH v2 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled

The patchset includes the patch to implement a private attribute named
"number_of_ways_enabled" in the cacheinfo framework. Reading this
attribute returns the number of L2 cache ways enabled at runtime,
The patchset also include the patch to add DT node for SiFive L2 cache
controller.

This patchset is based on Linux v5.5-rc3 and tested on HiFive Unleashed
board.

Changes in v2:
- Rebase the series on v5.5-rc3
- Remove the reserved-memory node from DT

Yash Shah (2):
  riscv: dts: Add DT support for SiFive L2 cache controller
  riscv: cacheinfo: Add support to determine no. of L2 cache way enabled

 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
 arch/riscv/include/asm/sifive_l2_cache.h   |  2 ++
 arch/riscv/kernel/cacheinfo.c              | 31 ++++++++++++++++++++++++++++++
 drivers/soc/sifive/sifive_l2_cache.c       |  5 +++++
 4 files changed, 53 insertions(+)

-- 
2.7.4