linux-kernel - Re: [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache controller

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Message-ID: <alpine.DEB.2.21.9999.2001031657090.283180@viisi.sifive.com>
Date:   Fri, 3 Jan 2020 16:57:21 -0800 (PST)
From:   Paul Walmsley <paul.walmsley@...ive.com>
To:     Yash Shah <yash.shah@...ive.com>
cc:     robh+dt@...nel.org, mark.rutland@....com, palmer@...belt.com,
        aou@...s.berkeley.edu, bmeng.cn@...il.com, green.wan@...ive.com,
        allison@...utok.net, alexios.zavras@...el.com,
        gregkh@...uxfoundation.org, tglx@...utronix.de, bp@...e.de,
        devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, sachin.ghadi@...ive.com
Subject: Re: [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache
 controller

On Fri, 3 Jan 2020, Yash Shah wrote:

> Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
> 
> Signed-off-by: Yash Shah <yash.shah@...ive.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@...gle.com>

Thanks, queued for v5.5-rc.


- Paul