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Message-Id: <20200105025215.2522-1-guoren@kernel.org>
Date: Sun, 5 Jan 2020 10:52:14 +0800
From: guoren@...nel.org
To: paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, Anup.Patel@....com, vincent.chen@...ive.com,
zong.li@...ive.com, greentime.hu@...ive.com, bmeng.cn@...il.com,
atish.patra@....com
Cc: linux-kernel@...r.kernel.org, linux-arch@...r.kernel.org,
arnd@...db.de, linux-csky@...r.kernel.org,
linux-riscv@...ts.infradead.org, Guo Ren <ren_guo@...ky.com>
Subject: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset
From: Guo Ren <ren_guo@...ky.com>
CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_msia register.
Signed-off-by: Guo Ren <ren_guo@...ky.com>
---
arch/riscv/kernel/head.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 797802c73dee..2227db63f895 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -251,7 +251,7 @@ ENTRY(reset_regs)
#ifdef CONFIG_FPU
csrr t0, CSR_MISA
andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
- bnez t0, .Lreset_regs_done
+ beqz t0, .Lreset_regs_done
li t1, SR_FS
csrs CSR_STATUS, t1
--
2.17.0
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