[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-Id: <20200105071438.F10452085B@mail.kernel.org>
Date: Sat, 04 Jan 2020 23:14:38 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
Masahiro Yamada <yamada.masahiro@...ionext.com>,
Michael Turquette <mturquette@...libre.com>
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Masami Hiramatsu <masami.hiramatsu@...aro.org>,
Jassi Brar <jaswinder.singh@...aro.org>,
Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
Subject: Re: [PATCH v2] clk: uniphier: Add SCSSI clock gate for each channel
Quoting Kunihiko Hayashi (2019-12-26 17:42:05)
> SCSSI has clock gates for each channel in the SoCs newer than Pro4,
> so this adds missing clock gates for channel 1, 2 and 3. And more, this
> moves MCSSI clock ID after SCSSI.
>
> Fixes: ff388ee36516 ("clk: uniphier: add clock frequency support for SPI")
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
> Acked-by: Masahiro Yamada <yamada.masahiro@...ionext.com>
> ---
Applied to clk-next
Powered by blists - more mailing lists