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Message-ID: <20200106130438.GC1955714@ulmo>
Date:   Mon, 6 Jan 2020 14:04:38 +0100
From:   Thierry Reding <thierry.reding@...il.com>
To:     Vidya Sagar <vidyas@...dia.com>
Cc:     lorenzo.pieralisi@....com, bhelgaas@...gle.com, robh+dt@...nel.org,
        jonathanh@...dia.com, andrew.murray@....com, kishon@...com,
        gustavo.pimentel@...opsys.com, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        kthota@...dia.com, mmaddireddy@...dia.com, sagar.tv@...il.com
Subject: Re: [PATCH V2 1/5] soc/tegra: bpmp: Update ABI header

On Fri, Jan 03, 2020 at 06:14:00PM +0530, Vidya Sagar wrote:
> Update the firmware header to support uninitialization of UPHY PLL
> when the PCIe controller is operating in endpoint mode and host cuts
> the PCIe reference clock.
> 
> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
> ---
> V2:
> * Changed Copyright year from 2019 to 2020
> 
>  include/soc/tegra/bpmp-abi.h | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)

Bjorn, Lorenzo,

subsequent patches in this series depend on this patch, so I think it'd
be best if you took this into the PCI tree along with the DT bindings
and the PCI driver changes, so:

Acked-by: Thierry Reding <treding@...dia.com>

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