lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20200108164609.GH32742@smile.fi.intel.com>
Date:   Wed, 8 Jan 2020 18:46:09 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc:     Darren Hart <dvhart@...radead.org>,
        Lee Jones <lee.jones@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H . Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        Zha Qipeng <qipeng.zha@...el.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...ux.intel.com>,
        "David E . Box" <david.e.box@...ux.intel.com>,
        Guenter Roeck <linux@...ck-us.net>,
        Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Wim Van Sebroeck <wim@...ux-watchdog.org>,
        platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 18/36] platform/x86: intel_pmc_ipc: Make
 intel_pmc_gcr_update() static

On Wed, Jan 08, 2020 at 02:41:43PM +0300, Mika Westerberg wrote:
> This function is not called outside of intel_pmc_ipc.c so we can make it
> static instead.
> 

Reviewed-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>

> Signed-off-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
> ---
>  arch/x86/include/asm/intel_pmc_ipc.h | 6 ------
>  drivers/platform/x86/intel_pmc_ipc.c | 3 +--
>  2 files changed, 1 insertion(+), 8 deletions(-)
> 
> diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h
> index 9e7adcdbe031..3b2e8b461520 100644
> --- a/arch/x86/include/asm/intel_pmc_ipc.h
> +++ b/arch/x86/include/asm/intel_pmc_ipc.h
> @@ -40,7 +40,6 @@ int intel_pmc_s0ix_counter_read(u64 *data);
>  int intel_pmc_gcr_read(u32 offset, u32 *data);
>  int intel_pmc_gcr_read64(u32 offset, u64 *data);
>  int intel_pmc_gcr_write(u32 offset, u32 data);
> -int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val);
>  
>  #else
>  
> @@ -81,11 +80,6 @@ static inline int intel_pmc_gcr_write(u32 offset, u32 data)
>  	return -EINVAL;
>  }
>  
> -static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
> -{
> -	return -EINVAL;
> -}
> -
>  #endif /*CONFIG_INTEL_PMC_IPC*/
>  
>  #endif
> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c
> index 5c1da2bb1435..9229c7a16536 100644
> --- a/drivers/platform/x86/intel_pmc_ipc.c
> +++ b/drivers/platform/x86/intel_pmc_ipc.c
> @@ -309,7 +309,7 @@ EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);
>   *
>   * Return:	negative value on error or 0 on success.
>   */
> -int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
> +static int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
>  {
>  	u32 new_val;
>  	int ret = 0;
> @@ -339,7 +339,6 @@ int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
>  	spin_unlock(&ipcdev.gcr_lock);
>  	return ret;
>  }
> -EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
>  
>  static int update_no_reboot_bit(void *priv, bool set)
>  {
> -- 
> 2.24.1
> 

-- 
With Best Regards,
Andy Shevchenko


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ