lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 8 Jan 2020 19:36:57 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc:     Darren Hart <dvhart@...radead.org>,
        Lee Jones <lee.jones@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H . Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        Zha Qipeng <qipeng.zha@...el.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...ux.intel.com>,
        "David E . Box" <david.e.box@...ux.intel.com>,
        Guenter Roeck <linux@...ck-us.net>,
        Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Wim Van Sebroeck <wim@...ux-watchdog.org>,
        platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 31/36] x86/platform/intel-mid: Add empty stubs for
 intel_scu_devices_[create|destroy]()

On Wed, Jan 08, 2020 at 02:41:56PM +0300, Mika Westerberg wrote:
> This allows to call the functions even when CONFIG_X86_INTEL_MID is not
> enabled.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>

> 
> Signed-off-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
> ---
>  arch/x86/include/asm/intel-mid.h | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h
> index 8e5af119dc2d..de58391bdee0 100644
> --- a/arch/x86/include/asm/intel-mid.h
> +++ b/arch/x86/include/asm/intel-mid.h
> @@ -88,11 +88,17 @@ static inline bool intel_mid_has_msic(void)
>  	return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
>  }
>  
> +extern void intel_scu_devices_create(void);
> +extern void intel_scu_devices_destroy(void);
> +
>  #else /* !CONFIG_X86_INTEL_MID */
>  
>  #define intel_mid_identify_cpu()	0
>  #define intel_mid_has_msic()		0
>  
> +static inline void intel_scu_devices_create(void) { }
> +static inline void intel_scu_devices_destroy(void) { }
> +
>  #endif /* !CONFIG_X86_INTEL_MID */
>  
>  enum intel_mid_timer_options {
> @@ -115,9 +121,6 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
>  #define SFI_MTMR_MAX_NUM		8
>  #define SFI_MRTC_MAX			8
>  
> -extern void intel_scu_devices_create(void);
> -extern void intel_scu_devices_destroy(void);
> -
>  /* VRTC timer */
>  #define MRST_VRTC_MAP_SZ		1024
>  /* #define MRST_VRTC_PGOFFSET		0xc00 */
> -- 
> 2.24.1
> 

-- 
With Best Regards,
Andy Shevchenko


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ