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Message-ID: <1578539400.20923.10.camel@mhfsdcap03>
Date: Thu, 9 Jan 2020 11:10:00 +0800
From: Yong Liang <yong.liang@...iatek.com>
To: Nicolas Boichat <drinkcat@...omium.org>
CC: Jiaxin Yu (俞家鑫)
<Jiaxin.Yu@...iatek.com>,
"wim@...ux-watchdog.org" <wim@...ux-watchdog.org>,
"linux@...ck-us.net" <linux@...ck-us.net>,
Philipp Zabel <p.zabel@...gutronix.de>,
Matthias Brugger <matthias.bgg@...il.com>,
"linux-watchdog@...r.kernel.org" <linux-watchdog@...r.kernel.org>,
lkml <linux-kernel@...r.kernel.org>,
linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Devicetree List <devicetree@...r.kernel.org>,
Chang-An Chen (陳昶安)
<Chang-An.Chen@...iatek.com>,
Freddy Hsin (辛恒豐)
<Freddy.Hsin@...iatek.com>,
Yingjoe Chen (陳英洲)
<Yingjoe.Chen@...iatek.com>, Stephen Boyd <sboyd@...nel.org>
Subject: Re: [PATCH v10 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells
On Wed, 2020-01-08 at 17:23 +0800, Nicolas Boichat wrote:
> On Mon, Jan 6, 2020 at 11:11 AM Jiaxin Yu <jiaxin.yu@...iatek.com> wrote:
> >
> > Add #reset-cells property and update example
> >
> > Signed-off-by: yong.liang <yong.liang@...iatek.com>
> > Signed-off-by: Jiaxin Yu <jiaxin.yu@...iatek.com>
> > Reviewed-by: Yingjoe Chen <yingjoe.chen@...iatek.com>
> > Reviewed-by: Philipp Zabel <p.zabel@...gutronix.de>
> > ---
> > .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 ++++++---
> > .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++
> > .../reset-controller/mt8183-resets.h | 17 ++++++++++++++
> > 3 files changed, 46 insertions(+), 3 deletions(-)
> > create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h
> >
> > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > index 92181b648f52..5a76ac262f8d 100644
> > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> > @@ -4,6 +4,7 @@ Required properties:
> >
> > - compatible should contain:
> > "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
> > + "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
>
> Doesn't look related?
We prefer to send mt2712 and mt8183 together.
>
> > "mediatek,mt6589-wdt": for MT6589
> > "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
> > "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
> > @@ -14,11 +15,14 @@ Required properties:
> >
> > Optional properties:
> > - timeout-sec: contains the watchdog timeout in seconds.
> > +- #reset-cells: Should be 1.
> >
> > Example:
> >
> > -wdt: watchdog@...00000 {
> > - compatible = "mediatek,mt6589-wdt";
> > - reg = <0x10000000 0x18>;
> > +watchdog: watchdog@...07000 {
> > + compatible = "mediatek,mt8183-wdt",
>
> Well mt8183-wdt compatible is not yet upstream, do you want to work
> with Yong Liang to send both these bindings in the same series? (you
> can add mt2712 in the same patch as mt8183 binding maybe?)
We prefer to send mt2712 and mt8183 together. And we want to send this
patch priority.
Yong.Liang
>
> > + "mediatek,mt6589-wdt";
> > + reg = <0 0x10007000 0 0x100>;
> > timeout-sec = <10>;
> > + #reset-cells = <1>;
> > };
> > diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h
> > new file mode 100644
> > index 000000000000..9e7ee762f076
> > --- /dev/null
> > +++ b/include/dt-bindings/reset-controller/mt2712-resets.h
> > @@ -0,0 +1,22 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2019 MediaTek Inc.
> > + * Author: Yong Liang <yong.liang@...iatek.com>
> > + */
> > +
> > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712
> > +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712
> > +
> > +#define MT2712_TOPRGU_INFRA_SW_RST 0
> > +#define MT2712_TOPRGU_MM_SW_RST 1
> > +#define MT2712_TOPRGU_MFG_SW_RST 2
> > +#define MT2712_TOPRGU_VENC_SW_RST 3
> > +#define MT2712_TOPRGU_VDEC_SW_RST 4
> > +#define MT2712_TOPRGU_IMG_SW_RST 5
> > +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8
> > +#define MT2712_TOPRGU_USB_SW_RST 9
> > +#define MT2712_TOPRGU_APMIXED_SW_RST 10
> > +
> > +#define MT2712_TOPRGU_SW_RST_NUM 11
> > +
> > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */
> > diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h
> > index 8804e34ebdd4..a1bbd41e0d12 100644
> > --- a/include/dt-bindings/reset-controller/mt8183-resets.h
> > +++ b/include/dt-bindings/reset-controller/mt8183-resets.h
> > @@ -78,4 +78,21 @@
> > #define MT8183_INFRACFG_AO_I2C7_SW_RST 126
> > #define MT8183_INFRACFG_AO_I2C8_SW_RST 127
> >
> > +#define MT8183_INFRACFG_SW_RST_NUM 128
> > +
> > +#define MT8183_TOPRGU_MM_SW_RST 1
> > +#define MT8183_TOPRGU_MFG_SW_RST 2
> > +#define MT8183_TOPRGU_VENC_SW_RST 3
> > +#define MT8183_TOPRGU_VDEC_SW_RST 4
> > +#define MT8183_TOPRGU_IMG_SW_RST 5
> > +#define MT8183_TOPRGU_MD_SW_RST 7
> > +#define MT8183_TOPRGU_CONN_SW_RST 9
> > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12
> > +#define MT8183_TOPRGU_IPU0_SW_RST 14
> > +#define MT8183_TOPRGU_IPU1_SW_RST 15
> > +#define MT8183_TOPRGU_AUDIO_SW_RST 17
> > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18
> > +
> > +#define MT8183_TOPRGU_SW_RST_NUM 19
> > +
> > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */
> > --
> > 2.18.0
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