linux-kernel - [RFC v5 27/57] objtool: arm64: Decode instruction triggering context switch

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Message-Id: <20200109160300.26150-28-jthierry@redhat.com>
Date:   Thu,  9 Jan 2020 16:02:30 +0000
From:   Julien Thierry <jthierry@...hat.com>
To:     linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Cc:     jpoimboe@...hat.com, peterz@...radead.org, raphael.gault@....com,
        catalin.marinas@....com, will@...nel.org,
        Julien Thierry <jthierry@...hat.com>
Subject: [RFC v5 27/57] objtool: arm64: Decode instruction triggering context switch

Decode instructions that volutarily trigger an exception to change
the context of execution.

Suggested-by: Raphael Gault <raphael.gault@....com>
Signed-off-by: Julien Thierry <jthierry@...hat.com>
---
 tools/objtool/arch/arm64/decode.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c
index 1609750cc4b9..5eba83c5d5bc 100644
--- a/tools/objtool/arch/arm64/decode.c
+++ b/tools/objtool/arch/arm64/decode.c
@@ -508,6 +508,10 @@ int arm_decode_except_gen(u32 instr, enum insn_type *type,
 #define INSN_HVC	0b00000010
 #define INSN_SMC	0b00000011
 #define INSN_BRK	0b00100000
+#define INSN_HLT	0b01000000
+#define INSN_DCPS1	0b10100001
+#define INSN_DCPS2	0b10100010
+#define INSN_DCPS3	0b10100011
 
 	switch (decode_field) {
 	case INSN_SVC:
@@ -551,6 +555,13 @@ int arm_decode_except_gen(u32 instr, enum insn_type *type,
 			break;
 		}
 		return 0;
+	case INSN_HLT:
+	case INSN_DCPS1:
+	case INSN_DCPS2:
+	case INSN_DCPS3:
+		*immediate = imm16;
+		*type = INSN_CONTEXT_SWITCH;
+		return 0;
 	default:
 		return arm_decode_unknown(instr, type, immediate, ops_list);
 	}
-- 
2.21.0