linux-kernel - Re: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset

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Message-ID: <alpine.DEB.2.21.9999.2001101730140.38813@viisi.sifive.com>
Date:   Fri, 10 Jan 2020 17:30:45 -0800 (PST)
From:   Paul Walmsley <paul.walmsley@...ive.com>
To:     guoren@...nel.org
cc:     palmer@...belt.com, aou@...s.berkeley.edu, Anup.Patel@....com,
        vincent.chen@...ive.com, zong.li@...ive.com,
        greentime.hu@...ive.com, bmeng.cn@...il.com, atish.patra@....com,
        linux-kernel@...r.kernel.org, linux-arch@...r.kernel.org,
        arnd@...db.de, linux-csky@...r.kernel.org,
        linux-riscv@...ts.infradead.org, Guo Ren <ren_guo@...ky.com>
Subject: Re: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset

On Sun, 5 Jan 2020, guoren@...nel.org wrote:

> From: Guo Ren <ren_guo@...ky.com>
> 
> CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
> ISA Register misa. Every bit:1 indicate a feature, so we should beqz
> reset_done when there is no F/D bit in csr_msia register.
> 
> Signed-off-by: Guo Ren <ren_guo@...ky.com>

Thanks Guo Ren, queued for v5.5-rc.


- Paul