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Date: Sat, 11 Jan 2020 10:50:12 +0100 From: Greg Kroah-Hartman <gregkh@...uxfoundation.org> To: linux-kernel@...r.kernel.org Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, stable@...r.kernel.org, Vitaly Slobodskoy <vitaly.slobodskoy@...el.com>, Alexander Shishkin <alexander.shishkin@...ux.intel.com>, "Peter Zijlstra (Intel)" <peterz@...radead.org>, Alexey Budankov <alexey.budankov@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>, Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...hat.com>, Sasha Levin <sashal@...nel.org> Subject: [PATCH 4.14 30/62] perf/x86/intel: Fix PT PMI handling From: Alexander Shishkin <alexander.shishkin@...ux.intel.com> [ Upstream commit 92ca7da4bdc24d63bb0bcd241c11441ddb63b80a ] Commit: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") skips the PT/LBR exclusivity check on CPUs where PT and LBRs coexist, but also inadvertently skips the active_events bump for PT in that case, which is a bug. If there aren't any hardware events at the same time as PT, the PMI handler will ignore PT PMIs, as active_events reads zero in that case, resulting in the "Uhhuh" spurious NMI warning and PT data loss. Fix this by always increasing active_events for PT events. Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") Reported-by: Vitaly Slobodskoy <vitaly.slobodskoy@...el.com> Signed-off-by: Alexander Shishkin <alexander.shishkin@...ux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org> Acked-by: Alexey Budankov <alexey.budankov@...ux.intel.com> Cc: Jiri Olsa <jolsa@...nel.org> Cc: Ingo Molnar <mingo@...hat.com> Cc: Arnaldo Carvalho de Melo <acme@...hat.com> Link: https://lkml.kernel.org/r/20191210105101.77210-1-alexander.shishkin@linux.intel.com Signed-off-by: Sasha Levin <sashal@...nel.org> --- arch/x86/events/core.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 6ed99de2ddf5..c1f7b3cb84a9 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -375,7 +375,7 @@ int x86_add_exclusive(unsigned int what) * LBR and BTS are still mutually exclusive. */ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) - return 0; + goto out; if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { mutex_lock(&pmc_reserve_mutex); @@ -387,6 +387,7 @@ int x86_add_exclusive(unsigned int what) mutex_unlock(&pmc_reserve_mutex); } +out: atomic_inc(&active_events); return 0; @@ -397,11 +398,15 @@ int x86_add_exclusive(unsigned int what) void x86_del_exclusive(unsigned int what) { + atomic_dec(&active_events); + + /* + * See the comment in x86_add_exclusive(). + */ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) return; atomic_dec(&x86_pmu.lbr_exclusive[what]); - atomic_dec(&active_events); } int x86_setup_perfctr(struct perf_event *event) -- 2.20.1
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