[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20200111094909.837271697@linuxfoundation.org>
Date: Sat, 11 Jan 2020 10:50:40 +0100
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, Anson Huang <Anson.Huang@....com>,
Shawn Guo <shawnguo@...nel.org>,
Sébastien Szymanski
<sebastien.szymanski@...adeus.com>,
Lucas Stach <l.stach@...gutronix.de>
Subject: [PATCH 4.19 63/84] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
From: Anson Huang <Anson.Huang@....com>
commit 92f0eb08c66a73594cf200e65689e767f7f0da5e upstream.
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.
Signed-off-by: Anson Huang <Anson.Huang@....com>
Signed-off-by: Shawn Guo <shawnguo@...nel.org>
Cc: Sébastien Szymanski <sebastien.szymanski@...adeus.com>
Cc: Lucas Stach <l.stach@...gutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -87,6 +87,8 @@
"pll1_sys";
arm-supply = <®_arm>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -930,6 +932,10 @@
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
lcdif: lcdif@...8000 {
Powered by blists - more mailing lists