linux-kernel - [PATCH 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 14 Jan 2020 00:43:30 +0800
From:   周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>
To:     linux-mips@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        robh+dt@...nel.org, paul.burton@...s.com, paulburton@...nel.org,
        jhogan@...nel.org, miquel.raynal@...tlin.com, mark.rutland@....com,
        syq@...ian.org, ralf@...ux-mips.org, tglx@...utronix.de,
        jason@...edaemon.net, maz@...nel.org, jiaxun.yang@...goat.com,
        chenhc@...ote.com, daniel.lezcano@...aro.org,
        ebiederm@...ssion.com, keescook@...omium.org, ak@...ux.intel.com,
        krzk@...nel.org, paul@...pouillou.net, prasannatsmkumar@...il.com,
        sernia.zhou@...mail.com, zhenwenjin@...il.com
Subject: [PATCH 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding.

Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
---
 .../bindings/mips/ingenic/ingenic,cpu.txt          | 32 ++++++++++++++++++++++
 .../bindings/mips/ingenic/ingenic,soc,txt          | 18 ++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
 create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt

diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
new file mode 100644
index 00000000..f23e9be
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
@@ -0,0 +1,32 @@
+Bindings for Ingenic XBurst family CPUs.
+
+Required properties:
+- device_type: Must be "cpu".
+- compatible: One of:
+  - "ingenic,xburst".
+  - "ingenic,xburst2".
+- reg: The number of the CPU.
+
+Example:
+cpus {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	cpu0: cpu@0 {
+		device_type = "cpu";
+		compatible = "ingenic,xburst";
+		reg = <0>;
+
+		clocks = <&cgu JZ4780_CLK_CPU>;
+		clock-names = "cpu";
+	};
+
+	cpu1: cpu@1 {
+		device_type = "cpu";
+		compatible = "ingenic,xburst";
+		reg = <1>;
+
+		clocks = <&cgu JZ4780_CLK_CORE1>;
+		clock-names = "cpu";
+	};
+};
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt
new file mode 100644
index 00000000..c731fa3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt
@@ -0,0 +1,18 @@
+Bindings for Ingenic SoCs with XBurst CPU inside.
+
+Required properties:
+- compatible: One of:
+  - "ingenic,jz4740".
+  - "ingenic,jz4725b".
+  - "ingenic,jz4760".
+  - "ingenic,jz4760b".
+  - "ingenic,jz4770".
+  - "ingenic,jz4780".
+  - "ingenic,x1000".
+  - "ingenic,x1000e".
+  - "ingenic,x1500".
+
+Example:
+#address-cells = <1>;
+#size-cells = <1>;
+compatible = "ingenic,jz4780";
-- 
2.7.4