Message-ID: <9177657a-71c7-7bd0-a981-3ef1f736d4dc@oracle.com>
Date:   Tue, 14 Jan 2020 10:06:06 -0800
From:   santosh.shilimkar@...cle.com
To:     Sekhar Nori <nsekhar@...com>,
        Peter Ujfalusi <peter.ujfalusi@...com>, vkoul@...nel.org,
        robh+dt@...nel.org, nm@...com, ssantosh@...nel.org
Cc:     dan.j.williams@...el.com, dmaengine@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, grygorii.strashko@...com,
        lokeshvutla@...com, t-kristo@...com, tony@...mide.com,
        j-keerthy@...com, vigneshr@...com, frowand.list@...il.com
Subject: Re: [PATCH v8 02/18] soc: ti: k3: add navss ringacc driver

On 1/14/20 12:11 AM, Sekhar Nori wrote:
> On 14/01/20 12:28 PM, Peter Ujfalusi wrote:
>> Hi Santosh,
>>
>> On 13/01/2020 23.28, santosh.shilimkar@...cle.com wrote:
>>>
>>>
>>> On 12/23/19 3:38 AM, Peter Ujfalusi wrote:
>>>> Hi Santosh,
>>>>
>>>> On 23/12/2019 13.04, Peter Ujfalusi wrote:
>>>>> From: Grygorii Strashko <grygorii.strashko@...com>
>>>>>
>>>>> The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
>>>>> enable straightforward passing of work between a producer and a
>>>>> consumer.
>>>>> There is one RINGACC module per NAVSS on TI AM65x SoCs.
>>>>>
>>>>> The RINGACC converts constant-address read and write accesses to
>>>>> equivalent
>>>>> read or write accesses to a circular data structure in memory. The
>>>>> RINGACC
>>>>> eliminates the need for each DMA controller which needs to access ring
>>>>> elements from having to know the current state of the ring (base
>>>>> address,
>>>>> current offset). The DMA controller performs a read or write access to a
>>>>> specific address range (which maps to the source interface on the
>>>>> RINGACC)
>>>>> and the RINGACC replaces the address for the transaction with a new
>>>>> address
>>>>> which corresponds to the head or tail element of the ring (head for
>>>>> reads,
>>>>> tail for writes). Since the RINGACC maintains the state, multiple DMA
>>>>> controllers or channels are allowed to coherently share the same
>>>>> rings as
>>>>> applicable. The RINGACC is able to place data which is destined towards
>>>>> software into cached memory directly.
>>>>>
>>>>> Supported ring modes:
>>>>> - Ring Mode
>>>>> - Messaging Mode
>>>>> - Credentials Mode
>>>>> - Queue Manager Mode
>>>>>
>>>>> TI-SCI integration:
>>>>>
>>>>> Texas Instrument's System Control Interface (TI-SCI) Message Protocol
>>>>> now
>>>>> has control over Ringacc module resources management (RM) and Rings
>>>>> configuration.
>>>>>
>>>>> The corresponding support of TI-SCI Ringacc module RM protocol
>>>>> introduced as option through DT parameters:
>>>>> - ti,sci: phandle on TI-SCI firmware controller DT node
>>>>> - ti,sci-dev-id: TI-SCI device identifier as per TI-SCI firmware spec
>>>>>
>>>>> if both parameters present - Ringacc driver will configure/free/reset
>>>>> Rings
>>>>> using TI-SCI Message Ringacc RM Protocol.
>>>>>
>>>>> The Ringacc driver manages Rings allocation by itself now and requests
>>>>> TI-SCI firmware to allocate and configure specific Rings only. It's done
>>>>> this way because, Linux driver implements two stage Rings allocation and
>>>>> configuration (allocate ring and configure ring) while TI-SCI Message
>>>>> Protocol supports only one combined operation (allocate+configure).
>>>>>
>>>>> Signed-off-by: Grygorii Strashko <grygorii.strashko@...com>
>>>>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@...com>
>>>>> Reviewed-by: Tero Kristo <t-kristo@...com>
>>>>> Tested-by: Keerthy <j-keerthy@...com>
>>>>
>>>> Can you please giver your Acked-by for the ringacc patches if they are
>>>> still OK from your point of view as you had offered to take them before
>>>> I got comments from Lokesh.
>>>>
>>> Sure. But you really need to split the series so that dma engine and
>>> soc driver patches can be applied independently.
>>
>> The ringacc is a build and runtime dependency for the DMA. I have hoped
>> that all of them can go via DMAengine (hence asking for your ACK on the
>> drivers/soc/ti/ patches) for 5.6.
>>
>>> Can you please do that?
>>
>> This late in the merge window that would really mean that I will miss
>> another release for the KS3 DMA...
>> I can live with that if you can pick the ringacc for 5.6 and if Vinod
>> takes the DMAengine core changes as well.
>>
>> That would leave only the DMA drivers for 5.7 and we can also queue up
>> changes for 5.7 which depends on the DMAengine API (ASoC changes, UART,
>> sa2ul, etc).
>>
>> If they go independently and nothing makes it to 5.6 then 5.8 is the
>> realistic target for the DMA support for the KS3 family of devices...
> 
> Thats too many kernel versions to get this important piece in.
> 
> Santosh, if you do not have anything else queued up that clashes with
> this, can the whole series be picked up by Vinod with your ack on the
> drivers/soc/ti/ pieces?
> 
I would prefer driver patches to go via driver tree.

> Vinod could also perhaps setup an immutable branch based on v5.5-rc1
> with just the drivers/soc/ti parts applied so you can merge that branch
> in case you end up having to send up anything that conflicts.
> 
As suggested on other email to Peter, these DMA engine related patches
should be queued up since they don't have any dependency. Based on
the status of that patchset, will take care of pulling in the driver
patches either for this merge window or early part of next merge window.

Regards,
Santosh

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