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Message-ID: <1578986667-16041-19-git-send-email-skomatineni@nvidia.com>
Date: Mon, 13 Jan 2020 23:24:23 -0800
From: Sowjanya Komatineni <skomatineni@...dia.com>
To: <skomatineni@...dia.com>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <broonie@...nel.org>,
<lgirdwood@...il.com>, <perex@...ex.cz>, <tiwai@...e.com>,
<digetx@...il.com>, <mperttunen@...dia.com>,
<gregkh@...uxfoundation.org>, <sboyd@...nel.org>,
<robh+dt@...nel.org>, <mark.rutland@....com>
CC: <pdeschrijver@...dia.com>, <pgaikwad@...dia.com>,
<spujar@...dia.com>, <josephl@...dia.com>,
<daniel.lezcano@...aro.org>, <mmaddireddy@...dia.com>,
<markz@...dia.com>, <devicetree@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH v8 18/22] ASoC: tegra: Add audio mclk parent configuration
Tegra PMC clock clk_out_1 is dedicated for audio mclk from Tegra30
through Tegra210 and currently Tegra clock driver does the initial parent
configuration for audio mclk and keeps it enabled by default.
With the move of PMC clocks from clock driver into pmc driver,
audio clocks parent configuration can be specified through the device tree
using assigned-clock-parents property and audio mclk control should be
taken care by the audio driver.
This patch has implementation for parent configuration when default parent
configuration through assigned-clock-parents property is not specified in
the device tree.
Tested-by: Dmitry Osipenko <digetx@...il.com>
Reviewed-by: Dmitry Osipenko <digetx@...il.com>
Reviewed-by: Sameer Pujar <spujar@...dia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
---
sound/soc/tegra/tegra_asoc_utils.c | 68 ++++++++++++++++++++++----------------
1 file changed, 40 insertions(+), 28 deletions(-)
diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
index 84c4f59df71f..1dce5ad6e665 100644
--- a/sound/soc/tegra/tegra_asoc_utils.c
+++ b/sound/soc/tegra/tegra_asoc_utils.c
@@ -60,8 +60,6 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
data->set_mclk = 0;
clk_disable_unprepare(data->clk_cdev1);
- clk_disable_unprepare(data->clk_pll_a_out0);
- clk_disable_unprepare(data->clk_pll_a);
err = clk_set_rate(data->clk_pll_a, new_baseclock);
if (err) {
@@ -77,18 +75,6 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
- err = clk_prepare_enable(data->clk_pll_a);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a: %d\n", err);
- return err;
- }
-
- err = clk_prepare_enable(data->clk_pll_a_out0);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
- return err;
- }
-
err = clk_prepare_enable(data->clk_cdev1);
if (err) {
dev_err(data->dev, "Can't enable cdev1: %d\n", err);
@@ -109,8 +95,6 @@ int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
int err;
clk_disable_unprepare(data->clk_cdev1);
- clk_disable_unprepare(data->clk_pll_a_out0);
- clk_disable_unprepare(data->clk_pll_a);
/*
* AC97 rate is fixed at 24.576MHz and is used for both the host
@@ -130,18 +114,6 @@ int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
- err = clk_prepare_enable(data->clk_pll_a);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a: %d\n", err);
- return err;
- }
-
- err = clk_prepare_enable(data->clk_pll_a_out0);
- if (err) {
- dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
- return err;
- }
-
err = clk_prepare_enable(data->clk_cdev1);
if (err) {
dev_err(data->dev, "Can't enable cdev1: %d\n", err);
@@ -158,6 +130,7 @@ EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_ac97_rate);
int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
struct device *dev)
{
+ struct clk *clk_out_1, *clk_extern1;
int ret;
data->dev = dev;
@@ -204,6 +177,45 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
dev_info(data->dev, "Falling back to extern1\n");
}
+ /*
+ * If clock parents are not set in DT, configure here to use clk_out_1
+ * as mclk and extern1 as parent for Tegra30 and higher.
+ */
+ if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
+ data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
+ dev_warn(data->dev,
+ "Configuring clocks for a legacy device-tree\n");
+ dev_warn(data->dev,
+ "Please update DT to use assigned-clock-parents\n");
+ clk_extern1 = devm_clk_get(dev, "extern1");
+ if (IS_ERR(clk_extern1)) {
+ dev_err(data->dev, "Can't retrieve clk extern1\n");
+ return PTR_ERR(clk_extern1);
+ }
+
+ ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0);
+ if (ret < 0) {
+ dev_err(data->dev,
+ "Set parent failed for clk extern1\n");
+ return ret;
+ }
+
+ clk_out_1 = devm_clk_get(dev, "pmc_clk_out_1");
+ if (IS_ERR(clk_out_1)) {
+ dev_err(data->dev, "Can't retrieve pmc_clk_out_1\n");
+ return PTR_ERR(clk_out_1);
+ }
+
+ ret = clk_set_parent(clk_out_1, clk_extern1);
+ if (ret < 0) {
+ dev_err(data->dev,
+ "Set parent failed for pmc_clk_out_1\n");
+ return ret;
+ }
+
+ data->clk_cdev1 = clk_out_1;
+ }
+
ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
if (ret)
return ret;
--
2.7.4
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