lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 15 Jan 2020 15:29:41 -0600
From:   Eddie James <eajames@...ux.ibm.com>
To:     linux-aspeed@...ts.ozlabs.org
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        mark.rutland@....com, jason@...edaemon.net, maz@...nel.org,
        robh+dt@...nel.org, tglx@...utronix.de, joel@....id.au,
        andrew@...id.au, eajames@...ux.ibm.com
Subject: [PATCH v6 03/12] ARM: dts: aspeed: ast2500: Add SCU interrupt controller

Add a node for the interrupt controller provided by the SCU.

Signed-off-by: Eddie James <eajames@...ux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@...id.au>
---
 arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index ebec0fa..1c40c8f 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -222,6 +222,13 @@
 				#clock-cells = <1>;
 				#reset-cells = <1>;
 
+				scu_ic: interrupt-controller@18 {
+					#interrupt-cells = <1>;
+					compatible = "aspeed,ast2500-scu-ic";
+					interrupts = <21>;
+					interrupt-controller;
+				};
+
 				p2a: p2a-control@2c {
 					compatible = "aspeed,ast2500-p2a-ctrl";
 					reg = <0x2c 0x4>;
-- 
1.8.3.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ