linux-kernel - Re: [PATCH v5 3/6] PCI: brcmstb: Add Broadcom STB PCIe host controller driver

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Message-ID: <be8ddb33a7360af1815cf686f77f3f0913d02be3.camel@suse.de>
Date:   Wed, 15 Jan 2020 12:29:37 +0100
From:   Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Cc:     andrew.murray@....com, maz@...nel.org,
        linux-kernel@...r.kernel.org,
        Florian Fainelli <f.fainelli@...il.com>,
        bcm-kernel-feedback-list@...adcom.com, james.quinlan@...adcom.com,
        mbrugger@...e.com, phil@...pberrypi.org, wahrenst@....net,
        jeremy.linton@....com, linux-pci@...r.kernel.org,
        linux-rpi-kernel@...ts.infradead.org,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v5 3/6] PCI: brcmstb: Add Broadcom STB PCIe host
 controller driver

On Wed, 2020-01-15 at 10:00 +0000, Lorenzo Pieralisi wrote:
> On Tue, Jan 14, 2020 at 07:18:46PM +0100, Nicolas Saenz Julienne wrote:
> > Hi Lorenzo,
> > 
> > On Tue, 2020-01-14 at 17:11 +0000, Lorenzo Pieralisi wrote:
> > > On Mon, Dec 16, 2019 at 12:01:09PM +0100, Nicolas Saenz Julienne wrote:
> > > > From: Jim Quinlan <james.quinlan@...adcom.com>
> > > > 
> > > > This adds a basic driver for Broadcom's STB PCIe controller, for now
> > > > aimed at Raspberry Pi 4's SoC, bcm2711.
> > > > 
> > > > Signed-off-by: Jim Quinlan <james.quinlan@...adcom.com>
> > > > Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
> > > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
> > > > Reviewed-by: Andrew Murray <andrew.murray@....com>
> > > > Reviewed-by: Jeremy Linton <jeremy.linton@....com>
> > > > 
> > > > ---
> > > > 
> > > > Changes since v3:
> > > >   - Update commit message
> > > >   - rollback roundup_pow_two usage, it'll be updated later down the line
> > > >   - Remove comment in register definition
> > > > 
> > > > Changes since v2:
> > > >   - Correct rc_bar2_offset sign
> > > 
> > > In relation to this change.
> > > 
> > > [...]
> > > 
> > > > +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct
> > > > brcm_pcie
> > > > *pcie,
> > > > +							u64
> > > > *rc_bar2_size,
> > > > +							u64
> > > > *rc_bar2_offset)
> > > > +{
> > > > +	struct pci_host_bridge *bridge =
> > > > pci_host_bridge_from_priv(pcie);
> > > > +	struct device *dev = pcie->dev;
> > > > +	struct resource_entry *entry;
> > > > +
> > > > +	entry = resource_list_first_type(&bridge->dma_ranges,
> > > > IORESOURCE_MEM);
> > > > +	if (!entry)
> > > > +		return -ENODEV;
> > > > +
> > > > +	*rc_bar2_offset = -entry->offset;
> > > 
> > > I think this deserves a comment - I guess it has to do with how the
> > > controller expects CPU<->PCI offsets to be expressed compared to how it
> > > is computed in dma_ranges entries.
> > 
> > You're right, OF code calculates it by doing:
> > 
> > 	offset = cpu_start_addr - pci_start_addr (see
> > devm_of_pci_get_host_bridge_resources())
> > 
> > While the RC_BAR2_CONFIG register expects the opposite subtraction.
> > I'll add a comment on the next revision.
> 
> There is no need for a new posting, either write that comment here
> and I update the code or inline the patch or just resend *this* updated
> patch to the list.

OK, hope this sounds good enough:

	/*
	 * The controller expects the inbound window offset to be calculated as
	 * the difference between PCIe's address space and CPU's. The offset
	 * provided by the firmware is calculated the opposite way, so we
	 * negate it.
	 */

Regards,
Nicolas


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