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Date: Fri, 17 Jan 2020 01:23:46 +0800
From: 周琰杰 (Zhou Yanjie)
<zhouyanjie@...yeetech.com>
To: linux-mips@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
mips-creator-ci20-dev@...glegroups.com, robh+dt@...nel.org,
paul.burton@...s.com, paulburton@...nel.org, jhogan@...nel.org,
mark.rutland@....com, syq@...ian.org, ralf@...ux-mips.org,
rick.tyliu@...enic.com, jason@...edaemon.net,
keescook@...omium.org, geert+renesas@...der.be, krzk@...nel.org,
paul@...pouillou.net, prasannatsmkumar@...il.com,
sernia.zhou@...mail.com, zhenwenjin@...il.com,
ebiederm@...ssion.com, hns@...delico.com, paul@...die.org.uk
Subject: [PATCH v2 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding.
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Tested-by: H. Nikolaus Schaller <hns@...delico.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
---
Notes:
v1->v2:
Change the two Document from txt to yaml.
.../bindings/mips/ingenic/ingenic,cpu.yaml | 53 ++++++++++++++++++++++
.../bindings/mips/ingenic/ingenic,soc,yaml | 35 ++++++++++++++
2 files changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
new file mode 100644
index 00000000..91041a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic XBurst family CPUs
+
+maintainers:
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
+description: |
+ Ingenic XBurst family CPUs shall have the following properties.
+
+properties:
+ compatible:
+ oneOf:
+ - "ingenic,xburst".
+ - "ingenic,xburst2".
+
+ reg:
+ description: |
+ The number of the CPU.
+
+required:
+ - device_type
+ - compatible
+ - reg
+
+Example:
+ - |
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+
+ clocks = <&cgu JZ4780_CLK_CPU>;
+ clock-names = "cpu";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <1>;
+
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ clock-names = "cpu";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml
new file mode 100644
index 00000000..6269da7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/ingenic,soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic SoCs with XBurst CPU inside.
+
+maintainers:
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
+description: |
+ Ingenic SoCs with XBurst CPU inside shall have the following properties.
+
+properties:
+ compatible:
+ oneOf:
+ - "ingenic,jz4740".
+ - "ingenic,jz4725b".
+ - "ingenic,jz4760".
+ - "ingenic,jz4760b".
+ - "ingenic,jz4770".
+ - "ingenic,jz4780".
+ - "ingenic,x1000".
+ - "ingenic,x1000e".
+ - "ingenic,x1500".
+
+required:
+ - compatible
+
+examples:
+ - |
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ingenic,jz4780";
+...
--
2.7.4
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