linux-kernel - Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register for sdmmc

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Message-ID: <2ce63f11-8b0c-8261-63fa-cd19e874c537@st.com>
Date:   Thu, 16 Jan 2020 10:20:26 +0100
From:   Ludovic BARRE <ludovic.barre@...com>
To:     Rob Herring <robh@...nel.org>
CC:     Ulf Hansson <ulf.hansson@...aro.org>,
        <srinivas.kandagatla@...aro.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-mmc@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>
Subject: Re: [PATCH 5/9] dt-bindings: mmc: mmci: add delay block base register
 for sdmmc

Hi Rob

Le 1/15/20 à 3:56 PM, Rob Herring a écrit :
> On Fri, Jan 10, 2020 at 02:48:19PM +0100, Ludovic Barre wrote:
>> To support the sdr104 mode, the sdmmc variant has a
>> hardware delay block to manage the clock phase when sampling
>> data received by the card.
>>
>> This patch adds a second base register (optional) for
>> sdmmc delay block.
>>
>> Signed-off-by: Ludovic Barre <ludovic.barre@...com>
>> ---
>>   Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt
>> index 6d3c626e017d..4ec921e4bf34 100644
>> --- a/Documentation/devicetree/bindings/mmc/mmci.txt
>> +++ b/Documentation/devicetree/bindings/mmc/mmci.txt
>> @@ -28,6 +28,8 @@ specific for ux500 variant:
>>   - st,sig-pin-fbclk       : feedback clock signal pin used.
>>   
>>   specific for sdmmc variant:
>> +- reg			 : a second base register may be defined if a delay
>> +                           block is present and used for tuning.
> 
> Which compatibles have a 2nd reg entry?

In fact, mmci driver is ARM Amba driver (arm,primecell) and has only one
compatible "arm,pl18x".
The variants are identified by primecell-periphid property
(discovered at runtime with HW block register or defined by
device tree property "arm,primecell-periphid").

The defaults "arm,pl18x" variants have only one base register,
but the SDMMC need a second base register for these
delay block registers.

example of sdmmc node:
	sdmmc1: sdmmc@...05000 {
		compatible = "arm,pl18x", "arm,primecell";
		arm,primecell-periphid = <0x00253180>;
		reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
	};

what do you advise?

> 
>>   - st,sig-dir             : signal direction polarity used for cmd, dat0 dat123.
>>   - st,neg-edge            : data & command phase relation, generated on
>>                              sd clock falling edge.
>> -- 
>> 2.17.1
>>