linux-kernel - Re: [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max virtual functions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <f0690395-4ce7-df93-e837-670829aafb03@ti.com>
Date:   Thu, 16 Jan 2020 16:59:20 +0530
From:   Kishon Vijay Abraham I <kishon@...com>
To:     Rob Herring <robh@...nel.org>
CC:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Andrew Murray <andrew.murray@....com>,
        Tom Joseph <tjoseph@...ence.com>,
        Arnd Bergmann <arnd@...db.de>,
        Jingoo Han <jingoohan1@...il.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Shawn Lin <shawn.lin@...k-chips.com>,
        Heiko Stuebner <heiko@...ech.de>, <linux-pci@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, Jonathan Corbet <corbet@....net>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        <linux-doc@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-rockchip@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max
 virtual functions

Hi Rob,

On 15/01/20 7:10 AM, Rob Herring wrote:
> On Tue, Dec 31, 2019 at 05:05:29PM +0530, Kishon Vijay Abraham I wrote:
>> Add binding to specify maximum number of virtual functions that can be
>> associated with each physical function.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
>> ---
>>  .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt         | 2 ++
>>  .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml          | 8 ++++++++
>>  2 files changed, 10 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
>> index 4a0475e2ba7e..432578202733 100644
>> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
>> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
>> @@ -9,6 +9,8 @@ Required properties:
>>  
>>  Optional properties:
>>  - max-functions: Maximum number of functions that can be configured (default 1).
>> +- max-virtual-functions: Maximum number of virtual functions that can be
>> +    associated with each physical function.
>>  - phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
>>    than one in the list.  If only one PHY listed it must manage all lanes. 
>>  - phy-names:  List of names to identify the PHY.
>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> index 4621c62016c7..1d4964ba494f 100644
>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
>> @@ -61,6 +61,12 @@ properties:
>>      minimum: 1
>>      maximum: 6
>>  
>> +  max-virtual-functions:
>> +    minItems: 1
>> +    maxItems: 6
> 
> Is there a PCIe spec limit to number of virtual functions per phy 
> function? Or 2^32 virtual functions is okay.

The PCIe spec provides a 16 bit field to specify number of virtual
functions in the SR-IOV extended capability.


> 
>> +    description: As defined in
>> +                 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
> 
> I suspect this this be a common property.

Right now we don't have common EP property binding across all
controllers. Maybe should create one?

Thanks
Kishon