linux-kernel - irqchip: Figuring out utility of hierarchy irqdomain

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Message-ID: <b27626dc-dad7-b19c-dcfd-f3668c5e5be6@elvees.com>
Date:   Thu, 16 Jan 2020 18:50:55 +0300
From:   Olga Kitaina <okitain@...ees.com>
To:     Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <maz@...nel.org>
Cc:     linux-kernel@...r.kernel.org
Subject: irqchip: Figuring out utility of hierarchy irqdomain

Hi, I'm looking to implement an interrupt controller (referred to here 
as QLIC) that is based on the RISC-V PLIC (see 
drivers/irqchip/irq-sifive-plic.c), with the difference that it's not 
the root interrupt controller, but instead it is connected to a GIC.

The features of the controller are as follows:

* A cluster of DSPs serve as interrupt sources to QLIC, each DSP with 
several interrupt lines going to QLIC.
* Several interrupt lines (documented as TARGET_x) go from QLIC to the GIC.
* Sources are mapped to targets by way of writing a mask of allowed 
sources in the TARG_x_ENABLE register.
* The source of an interrupt mapped to TARGET_x can be determined by 
reading from register TARG_x_CC. Writing the number of the source to 
TARG_x_CC masks the interrupt.
* To mask all interrupts corresponding to TARGET_x, TARG_x_CC must be 
read repeatedly, with the values written back after the source interrupt 
is handled.
* Source numbers start from 1, 0 is a special case in TARG_x_CC - it 
corresponds to "no interrupt", and writing 0 to the register does nothing.

I am not yet well-acquainted with the irq subsystem, which means I am 
not sure what kind of APIs I need to use. This is why I have a couple of 
questions:
1. Do I understand correctly that using hierarchy irqdomain means that 
the interrupt controller has to have a 1:1 mapping between inputs and 
outputs?
2. Is a chained handler necessary for this setup, e.g. handling 0 in 
TARG_x_CC?

-- 
Regards,
Olga