linux-kernel - Re: [PATCH v1 1/2] genirq: Check for level based percpu irq

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Message-Id: <1440861579227825@sas1-e05fd3bc78f9.qloud-c.yandex.net>
Date:   Fri, 17 Jan 2020 10:23:45 +0800
From:   Jiaxun Yang <jiaxun.yang@...goat.com>
To:     Thomas Gleixner <tglx@...utronix.de>,
        "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>
Cc:     "chenhc@...ote.com" <chenhc@...ote.com>,
        "paul.burton@...s.com" <paul.burton@...s.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "maz@...nel.org" <maz@...nel.org>
Subject: Re: [PATCH v1 1/2] genirq: Check for level based percpu irq



17.01.2020, 09:29, "Thomas Gleixner" <tglx@...utronix.de>:
> Jiaxun Yang <jiaxun.yang@...goat.com> writes:
>>  MIPS processors implemented their IPI IRQ and CPU interrupt line
>>  as level triggered IRQ. However, our current percpu_irq flow is trying
>>  do it in a level triggered manner.
>

Hi Thomas,

Thanks for your kind explanation.

That appears to be my misunderstanding of the trigger type.

Paul, I have confirmed it seems fine to handle percpu IRQ without mask
it on both Ingenic and Loongson processors. How about other MIPS Cores?
Could you please help check that?

Thanks.

--
Jiaxun Yang