linux-kernel - Re: [PATCH V3 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite

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Message-ID: <VI1PR04MB7023C33CB9D5EEFB094BF1ADEE320@VI1PR04MB7023.eurprd04.prod.outlook.com>
Date:   Mon, 20 Jan 2020 13:41:13 +0000
From:   Leonard Crestez <leonard.crestez@....com>
To:     Peng Fan <peng.fan@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>
CC:     "sboyd@...nel.org" <sboyd@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        Abel Vesa <abel.vesa@....com>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>,
        Aisheng Dong <aisheng.dong@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Anson Huang <anson.huang@....com>,
        Jacky Bai <ping.bai@....com>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>
Subject: Re: [PATCH V3 1/4] clk: imx: composite-8m: add
 imx8m_clk_hw_composite_core

On 16.01.2020 04:15, Peng Fan wrote:
> From: Peng Fan <peng.fan@....com>
> 
> There are several clock slices, current composite code
> only support bus/ip clock slices, it could not support core
> slice.
> 
> So introduce a new API imx8m_clk_hw_composite_core to support
> core slice. To core slice, post divider with 3 bits width and
> no pre divider. Other fields are same as bus/ip slices.
> 
> Add a flag IMX_COMPOSITE_CORE for the usecase.
> 
> Reviewed-by: Abel Vesa <abel.vesa@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>

Reviewed-by: Leonard Crestez <leonard.crestez@....com>

> ---
>   drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++----
>   drivers/clk/imx/clk.h              | 13 +++++++++++--
>   2 files changed, 25 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
> index e0f25983e80f..4174506e8bdd 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -15,6 +15,7 @@
>   #define PCG_PREDIV_MAX		8
>   
>   #define PCG_DIV_SHIFT		0
> +#define PCG_CORE_DIV_WIDTH	3
>   #define PCG_DIV_WIDTH		6
>   #define PCG_DIV_MAX		64
>   
> @@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
>   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   					const char * const *parent_names,
>   					int num_parents, void __iomem *reg,
> +					u32 composite_flags,
>   					unsigned long flags)
>   {
>   	struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
> @@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   	struct clk_divider *div = NULL;
>   	struct clk_gate *gate = NULL;
>   	struct clk_mux *mux = NULL;
> +	const struct clk_ops *divider_ops;
>   
>   	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
>   	if (!mux)
> @@ -149,8 +152,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   
>   	div_hw = &div->hw;
>   	div->reg = reg;
> -	div->shift = PCG_PREDIV_SHIFT;
> -	div->width = PCG_PREDIV_WIDTH;
> +	if (composite_flags & IMX_COMPOSITE_CORE) {
> +		div->shift = PCG_DIV_SHIFT;
> +		div->width = PCG_CORE_DIV_WIDTH;
> +		divider_ops = &clk_divider_ops;
> +	} else {
> +		div->shift = PCG_PREDIV_SHIFT;
> +		div->width = PCG_PREDIV_WIDTH;
> +		divider_ops = &imx8m_clk_composite_divider_ops;
> +	}
> +
>   	div->lock = &imx_ccm_lock;
>   	div->flags = CLK_DIVIDER_ROUND_CLOSEST;
>   
> @@ -164,8 +175,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   
>   	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
>   			mux_hw, &clk_mux_ops, div_hw,
> -			&imx8m_clk_composite_divider_ops,
> -			gate_hw, &clk_gate_ops, flags);
> +			divider_ops, gate_hw, &clk_gate_ops, flags);
>   	if (IS_ERR(hw))
>   		goto fail;
>   
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index b05213b91dcf..f074dd8ec42e 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
>   		struct clk *div, struct clk *mux, struct clk *pll,
>   		struct clk *step);
>   
> +#define IMX_COMPOSITE_CORE	BIT(0)
> +
>   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
>   					    const char * const *parent_names,
>   					    int num_parents,
>   					    void __iomem *reg,
> +					    u32 composite_flags,
>   					    unsigned long flags);
>   
> +#define imx8m_clk_hw_composite_core(name, parent_names, reg)	\
> +	imx8m_clk_hw_composite_flags(name, parent_names, \
> +			ARRAY_SIZE(parent_names), reg, \
> +			IMX_COMPOSITE_CORE, \
> +			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
> +
>   #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
>   				  flags) \
>   	to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
> -				num_parents, reg, flags))
> +				num_parents, reg, 0, flags))
>   
>   #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
>   	imx8m_clk_hw_composite_flags(name, parent_names, \
> -		ARRAY_SIZE(parent_names), reg, \
> +		ARRAY_SIZE(parent_names), reg, 0, \
>   		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
>   
>   #define __imx8m_clk_composite(name, parent_names, reg, flags) \
>