linux-kernel - Re: [PATCH v8 22/22] clk: tegra: Remove audio clocks configuration from clock driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <f2506b91-0199-f2a5-ea8c-ace7b651b443@gmail.com>
Date:   Tue, 21 Jan 2020 19:57:53 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Sowjanya Komatineni <skomatineni@...dia.com>,
        thierry.reding@...il.com, jonathanh@...dia.com, broonie@...nel.org,
        lgirdwood@...il.com, perex@...ex.cz, tiwai@...e.com,
        mperttunen@...dia.com, gregkh@...uxfoundation.org,
        sboyd@...nel.org, robh+dt@...nel.org, mark.rutland@....com
Cc:     pdeschrijver@...dia.com, pgaikwad@...dia.com, spujar@...dia.com,
        josephl@...dia.com, daniel.lezcano@...aro.org,
        mmaddireddy@...dia.com, markz@...dia.com,
        devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v8 22/22] clk: tegra: Remove audio clocks configuration
 from clock driver

21.01.2020 19:19, Sowjanya Komatineni пишет:
> 
> On 1/19/20 7:04 AM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 14.01.2020 10:24, Sowjanya Komatineni пишет:
>>
>> [snip]
>>
>>> diff --git a/drivers/clk/tegra/clk-tegra30.c
>>> b/drivers/clk/tegra/clk-tegra30.c
>>> index 5732fdbe20db..53d1c48532ae 100644
>>> --- a/drivers/clk/tegra/clk-tegra30.c
>>> +++ b/drivers/clk/tegra/clk-tegra30.c
>>> @@ -1221,9 +1221,8 @@ static struct tegra_clk_init_table init_table[]
>>> __initdata = {
>>>        { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
>>>        { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
>>>        { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
>>> -     { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
>>> -     { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
>>> -     { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
>>> +     { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
>>> +     { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
>>>        { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
>>>        { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
>>>        { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
>>>
>> What about to use the assigned-clock-rates in device-tree and thus to
>> remove those PLL_A entries?
> 
> Yes clock rates can be used and also PLL rate is set based on sample
> rate during hw_params. So this can be removed.
> 
> But PLLA clock rates are not related to this patch series and also
> changing this needs audio function testing across all platforms and
> currently we don't have audio functional tests in place for older
> platforms.
> 
> All audio clocks proper fixes and cleanup b/w clock driver and audio
> driver will be done separately.

If there are real plans to make sound driver to drive the PLLA rate,
then indeed should be fine to keep it as-is for now.