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Date: Wed, 22 Jan 2020 10:26:15 +0200
From: Peter Ujfalusi <peter.ujfalusi@...com>
To: <t-kristo@...com>, <nm@...com>
CC: <robh+dt@...nel.org>, <mark.rutland@....com>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v2 3/9] arm64: dts: ti: k3-am65: DMA support
Add the ringacc and udmap nodes for main and mcu NAVSS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@...com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 39 ++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 46 ++++++++++++++++++++++++
2 files changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index a125d66dd552..be841fc44b76 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -379,6 +379,10 @@ cbass_main_navss: navss@...00000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-coherent;
+ dma-ranges;
+
+ ti,sci-dev-id = <118>;
intr_main_navss: interrupt-controller1 {
compatible = "ti,sci-intr";
@@ -527,6 +531,41 @@ mailbox0_cluster11: mailbox@...8b000 {
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
};
+
+ ringacc: ringacc@...00000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <818>;
+ ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
+ ti,dma-ring-reset-quirk;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <187>;
+ msi-parent = <&inta_main_udmass>;
+ };
+
+ main_udmap: dma-controller@...50000 {
+ compatible = "ti,am654-navss-main-udmap";
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&inta_main_udmass>;
+ #dma-cells = <1>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <188>;
+ ti,ringacc = <&ringacc>;
+
+ ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
+ <0x2>; /* TX_CHAN */
+ ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
+ <0x5>; /* RX_CHAN */
+ ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
+ };
};
main_gpio0: main_gpio0@...000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 319e821b3c27..e32b3cbb4b25 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -104,6 +104,52 @@ adc {
};
};
+ cbass_mcu_navss: navss@...80000 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+ dma-ranges;
+
+ ti,sci-dev-id = <119>;
+
+ mcu_ringacc: ringacc@...00000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <286>;
+ ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
+ ti,dma-ring-reset-quirk;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <195>;
+ msi-parent = <&inta_main_udmass>;
+ };
+
+ mcu_udmap: dma-controller@...c0000 {
+ compatible = "ti,am654-navss-mcu-udmap";
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&inta_main_udmass>;
+ #dma-cells = <1>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <194>;
+ ti,ringacc = <&mcu_ringacc>;
+
+ ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
+ <0x2>; /* TX_CHAN */
+ ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
+ <0x4>; /* RX_CHAN */
+ ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
+ };
+ };
+
fss: fss@...00000 {
compatible = "simple-bus";
#address-cells = <2>;
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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