linux-kernel - Re: [PATCH 1/3] clk: rockchip: convert rk3399 pll type to use readl_poll

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 28 Jan 2020 17:29:05 +0100
From:   Heiko Stuebner <heiko@...ech.de>
To:     Robin Murphy <robin.murphy@....com>
Cc:     linux-clk@...r.kernel.org, sboyd@...nel.org,
        mturquette@...libre.com, zhangqing@...k-chips.com,
        linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org,
        christoph.muellner@...obroma-systems.com
Subject: Re: [PATCH 1/3] clk: rockchip: convert rk3399 pll type to use readl_poll_timeout

Am Dienstag, 28. Januar 2020, 16:28:44 CET schrieb Robin Murphy:
> On 28/01/2020 10:02 am, Heiko Stuebner wrote:
> > From: Heiko Stuebner <heiko.stuebner@...obroma-systems.com>
> > 
> > Instead of open coding the polling of the lock status, use the
> > handy readl_poll_timeout for this. As the pll locking is normally
> > blazingly fast and we don't want to incur additional delays, we're
> > not doing any sleeps similar to for example the imx clk-pllv4
> > and define a very safe but still short timeout of 1ms.
> > 
> > Suggested-by: Stephen Boyd <sboyd@...nel.org>
> > Signed-off-by: Heiko Stuebner <heiko.stuebner@...obroma-systems.com>
> > ---
> >   drivers/clk/rockchip/clk-pll.c | 21 ++++++++++-----------
> >   1 file changed, 10 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
> > index 198417d56300..43c9fd0086a2 100644
> > --- a/drivers/clk/rockchip/clk-pll.c
> > +++ b/drivers/clk/rockchip/clk-pll.c
> > @@ -585,19 +585,18 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
> >   static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
> >   {
> >   	u32 pllcon;
> > -	int delay = 24000000;
> > +	int ret;
> >   
> > -	/* poll check the lock status in rk3399 xPLLCON2 */
> > -	while (delay > 0) {
> > -		pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
> > -		if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
> > -			return 0;
> > +	/*
> > +	 * Lock time typical 250, max 500 input clock cycles @24MHz
> > +	 * So define a very safe maximum of 1000us, meaning 24000 cycles.
> > +	 */
> > +	ret = readl_poll_timeout(pll->reg_base + RK3399_PLLCON(2), pllcon,
> > +				 pllcon & RK3399_PLLCON2_LOCK_STATUS, 0, 1000);
> 
> Note that the existing I/O accessor was readl_relaxed(), but using plain 
> readl_poll_timeout() switches it to regular readl(). It may well not 
> matter, but since it's not noted as an intentional change it seemed 
> worth pointing out.

So we end up with an additional __iormb() after each readl_relaxed call.
So except for a small speed-penalty per iteration is there some other
memory-barrier wirednes that could come into play? (Somehow I always
forget the contents of Will's memory-barrier talks after a time)


>From a bit of non-scientific testing, rk3328 seems to need at max 20
iterations in the wait_lock loop for the pll to lock, when doing cpufreq
scaling.

While interestingly px30 takes somewhere between 900 and 2000 iterations
on the same pll type.
[Though sleeps are not really possible anyway due to pll rates also getting
set during of_clk_register early during boot which results in errors about
scheduling the idle thread, so in the end it doesn't really matter]

Heiko