linux-kernel - Re: [PATCH] clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate

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Message-ID: <3b8acaa8-8bc4-cc7f-51d1-2a1b4ff5374a@codeaurora.org>
Date:   Wed, 29 Jan 2020 08:51:19 +0530
From:   Rajendra Nayak <rnayak@...eaurora.org>
To:     Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>
Cc:     linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH] clk: qcom: Don't overwrite 'cfg' in
 clk_rcg2_dfs_populate_freq()


On 1/29/2020 1:03 AM, Stephen Boyd wrote:
> The DFS frequency table logic overwrites 'cfg' while detecting the
> parent clk and then later on in clk_rcg2_dfs_populate_freq() we use that
> same variable to figure out the mode of the clk, either MND or not. Add
> a new variable to hold the parent clk bit so that 'cfg' is left
> untouched for use later.
> 
> This fixes problems in detecting the supported frequencies for any clks
> in DFS mode.
> 
> Fixes: cc4f6944d0e3 ("clk: qcom: Add support for RCG to register for DFS")
> Reported-by: Rajendra Nayak <rnayak@...eaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@...nel.org>
> ---

Tested-by: Rajendra Nayak <rnayak@...eaurora.org>

>   drivers/clk/qcom/clk-rcg2.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index da045b200def..973ecf4f6bc5 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -953,7 +953,7 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
>   	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
>   	struct clk_hw *p;
>   	unsigned long prate = 0;
> -	u32 val, mask, cfg, mode;
> +	u32 val, mask, cfg, mode, src;
>   	int i, num_parents;
>   
>   	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
> @@ -963,12 +963,12 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
>   	if (cfg & mask)
>   		f->pre_div = cfg & mask;
>   
> -	cfg &= CFG_SRC_SEL_MASK;
> -	cfg >>= CFG_SRC_SEL_SHIFT;
> +	src = cfg & CFG_SRC_SEL_MASK;
> +	src >>= CFG_SRC_SEL_SHIFT;
>   
>   	num_parents = clk_hw_get_num_parents(hw);
>   	for (i = 0; i < num_parents; i++) {
> -		if (cfg == rcg->parent_map[i].cfg) {
> +		if (src == rcg->parent_map[i].cfg) {
>   			f->src = rcg->parent_map[i].src;
>   			p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
>   			prate = clk_hw_get_rate(p);
> 

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