linux-kernel - Re: [PATCH] riscv: set pmp configuration if kernel is running in M-mode

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Message-ID: <mhng-f4b42a19-22f3-43f3-9750-58b994e23246@palmerdabbelt-glaptop1>
Date:   Wed, 29 Jan 2020 11:23:26 -0800 (PST)
From:   Palmer Dabbelt <palmerdabbelt@...gle.com>
To:     greentime.hu@...ive.com
CC:     green.hu@...il.com, greentime@...nel.org,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        greentime.hu@...ive.com
Subject:     Re: [PATCH] riscv: set pmp configuration if kernel is running in M-mode

On Thu, 09 Jan 2020 03:17:40 GMT (+0000), greentime.hu@...ive.com wrote:
> When the kernel is running in S-mode, the expectation is that the
> bootloader or SBI layer will configure the PMP to allow the kernel to
> access physical memory.  But, when the kernel is running in M-mode and is
> started with the ELF "loader", there's probably no bootloader or SBI layer
> involved to configure the PMP.  Thus, we need to configure the PMP
> ourselves to enable the kernel to access all regions.
>
> Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
> ---
>  arch/riscv/include/asm/csr.h | 12 ++++++++++++
>  arch/riscv/kernel/head.S     |  6 ++++++
>  2 files changed, 18 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 0a62d2d68455..0f25e6c4e45c 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -72,6 +72,16 @@
>  #define EXC_LOAD_PAGE_FAULT	13
>  #define EXC_STORE_PAGE_FAULT	15
>
> +/* PMP configuration */
> +#define PMP_R			0x01
> +#define PMP_W			0x02
> +#define PMP_X			0x04
> +#define PMP_A			0x18
> +#define PMP_A_TOR		0x08
> +#define PMP_A_NA4		0x10
> +#define PMP_A_NAPOT		0x18
> +#define PMP_L			0x80
> +
>  /* symbolic CSR names: */
>  #define CSR_CYCLE		0xc00
>  #define CSR_TIME		0xc01
> @@ -100,6 +110,8 @@
>  #define CSR_MCAUSE		0x342
>  #define CSR_MTVAL		0x343
>  #define CSR_MIP			0x344
> +#define CSR_PMPCFG0		0x3a0
> +#define CSR_PMPADDR0		0x3b0
>  #define CSR_MHARTID		0xf14
>
>  #ifdef CONFIG_RISCV_M_MODE
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 5c8b24bf4e4e..f8f996916c5b 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -60,6 +60,12 @@ _start_kernel:
>  	/* Reset all registers except ra, a0, a1 */
>  	call reset_regs
>
> +	/* Setup a PMP to permit access to all of memory. */
> +	li a0, -1
> +	csrw CSR_PMPADDR0, a0
> +	li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
> +	csrw CSR_PMPCFG0, a0

These should be guarded by some sort of #ifdef CONFIG_M_MODE, as they're not
part of S mode.

> +
>  	/*
>  	 * The hartid in a0 is expected later on, and we have no firmware
>  	 * to hand it to us.