linux-kernel - Re: [PATCH 3/3] x86/tsc_msr: Make MSR derived TSC frequency more accurate

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Date:   Thu, 30 Jan 2020 17:59:19 +0100
From:   Hans de Goede <hdegoede@...hat.com>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     David Laight <David.Laight@...lab.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Andy Shevchenko <andy@...radead.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        Vipul Kumar <vipulk0511@...il.com>,
        Vipul Kumar <vipul_kumar@...tor.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Srikanth Krishnakar <Srikanth_Krishnakar@...tor.com>,
        Cedric Hombourger <Cedric_Hombourger@...tor.com>,
        Len Brown <len.brown@...el.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: Re: [PATCH 3/3] x86/tsc_msr: Make MSR derived TSC frequency more
 accurate

Hi,

On 30-01-2020 17:52, Andy Shevchenko wrote:
> On Thu, Jan 30, 2020 at 6:04 PM Hans de Goede <hdegoede@...hat.com> wrote:
>> On 30-01-2020 17:02, David Laight wrote:
> 
>> I have no idea. Andy if you can find any docs on the MSR_FSB_FREQ values
>> for Merriefield (BYT MID) and Moorefield (CHT MID) that would be great,
>> if not I suggest we stick with what we have.
> 
> First of all, Merrifield (Silvermont based Atom for phones, FYI: Intel
> Edison uses it) and Moorefield (Airmont) have nothing to do with code
> names Baytrail and Cherrytrail respectively.
> So, please don't confuse people.

Ok, sorry, I've prepped a v2 of this patch in my local tree with
the following changelog:

Changes in v2:
-Do not refer to Merrifield / Moorefield as BYT / CHT, they only share the
  CPU core design and otherwise are significantly different

> I'll try to find some information.

OK, I'll wait a bit with sending out the v2 then.

Regards,

Hans