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Date:   Thu, 30 Jan 2020 10:08:55 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Michael Turquette <mturquette@...libre.com>,
        Taniya Das <tdas@...eaurora.org>
Cc:     David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Andy Gross <agross@...nel.org>, devicetree@...r.kernel.org,
        robh@...nel.org, robh+dt@...nel.org,
        Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v3 3/3] clk: qcom: Add modem clock controller driver for SC7180

Quoting Taniya Das (2020-01-29 20:18:43)
> Add support for the modem clock controller found on SC7180
> based devices. This would allow modem drivers to probe and
> control their clocks.
> 
> Signed-off-by: Taniya Das <tdas@...eaurora.org>
> ---
>  drivers/clk/qcom/Kconfig      |   9 +++
>  drivers/clk/qcom/Makefile     |   1 +
>  drivers/clk/qcom/gcc-sc7180.c |  70 +++++++++++++++++++++
>  drivers/clk/qcom/mss-sc7180.c | 143 ++++++++++++++++++++++++++++++++++++++++++

Please split this patch into two, one for gcc and one for mss.

>  4 files changed, 223 insertions(+)
>  create mode 100644 drivers/clk/qcom/mss-sc7180.c
> 
> diff --git a/drivers/clk/qcom/mss-sc7180.c b/drivers/clk/qcom/mss-sc7180.c
> new file mode 100644
> index 0000000..d82600e
> --- /dev/null
> +++ b/drivers/clk/qcom/mss-sc7180.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,mss-sc7180.h>
> +
> +#include "clk-regmap.h"
> +#include "clk-branch.h"
> +#include "common.h"
> +
[...]
> +
> +static struct regmap_config mss_regmap_config = {

Can this be const?

> +       .reg_bits       = 32,
> +       .reg_stride     = 4,
> +       .val_bits       = 32,
> +       .fast_io        = true,
> +};
> +

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