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Date: Fri, 31 Jan 2020 11:33:03 +0000 From: David Laight <David.Laight@...LAB.COM> To: 'Bjorn Helgaas' <helgaas@...nel.org>, Muni Sekhar <munisekharrms@...il.com> CC: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org> Subject: RE: pcie: xilinx: kernel hang - ISR readl() From: Bjorn Helgaas > Sent: 30 January 2020 19:01 .. > > > You could learn this either via a PCIe analyzer (expensive piece of > > > hardware) or possibly some logic in the FPGA that would log PCIe > > > transactions in a buffer and make them accessible via some other > > > interface (you mentioned it had parallel and other interfaces). You can probably use the Xilinx equivalent of Altera 'signaltap' to work out what is happening within the fpga. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
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