linux-kernel - Re: [PATCH v6 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30

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Date:   Sat, 01 Feb 2020 23:57:42 +0100
From:   Marcel Ziswiler <marcel@...wiler.com>
To:     Dmitry Osipenko <digetx@...il.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Peter Geis <pgwipeout@...il.com>,
        Nicolas Chauvet <kwizart@...il.com>
Cc:     linux-pm@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 07/12] ARM: tegra: Don't enable PLLX while resuming
 from LP1 on Tegra30

Hi Dmitry

Finally, I came around giving this a try again on the Colibri T20 and
Apalis/Colibri T30.

Overall, works like a charm and you may add the following to the entire
series:

On Wed, 2019-12-18 at 23:21 +0300, Dmitry Osipenko wrote:
> PLLX may be kept disabled if cpufreq driver selects some other clock
> for
> CPU. In that case PLLX will be disabled later in the resume path by
> the
> CLK driver, which also can enable PLLX if necessary by itself. Thus
> there
> is no need to enable PLLX early during resume. Tegra114/124 CLK
> drivers do
> not manage PLLX on resume and thus they are left untouched by this
> patch.
> 
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>

Tested-by: Marcel Ziswiler <marcel@...wiler.com>
Tested-on: Colibri T20, Apalis/Colibri T30 on resp. EvalBoards

> ---
>  arch/arm/mach-tegra/sleep-tegra30.S | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-
> tegra/sleep-tegra30.S
> index 9a20c93abe48..4f073869b8ac 100644
> --- a/arch/arm/mach-tegra/sleep-tegra30.S
> +++ b/arch/arm/mach-tegra/sleep-tegra30.S
> @@ -358,7 +358,6 @@ _no_pll_iddq_exit:
>  
>  	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
>  	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
> -	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
>  
>  _pll_m_c_x_done:
>  	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
> @@ -368,8 +367,18 @@ _pll_m_c_x_done:
>  	pll_locked r1, r0, CLK_RESET_PLLP_BASE
>  	pll_locked r1, r0, CLK_RESET_PLLA_BASE
>  	pll_locked r1, r0, CLK_RESET_PLLC_BASE
> +
> +	/*
> +	 * CPUFreq driver could select other PLL for CPU. PLLX will be
> +	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
> +	 * tegra30_cpu_clock_resume().
> +	 */
> +	cmp	r10, #TEGRA30
> +	beq	_pll_m_c_x_locked
> +
>  	pll_locked r1, r0, CLK_RESET_PLLX_BASE
>  
> +_pll_m_c_x_locked:
>  	mov32	r7, TEGRA_TMRUS_BASE
>  	ldr	r1, [r7]
>  	add	r1, r1, #LOCK_DELAY

Unfortunately, that one does no longer apply after the following patch
recently got applied on Wed Jan 8:

commit 1a3388d506bf ("ARM: tegra: Enable PLLP bypass during Tegra124
LP1")

Thanks!

Cheers

Marcel