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Message-Id: <20200203103049.v4.6.If590c468722d2985cea63adf60c0d2b3098f37d9@changeid>
Date: Mon, 3 Feb 2020 10:31:39 -0800
From: Douglas Anderson <dianders@...omium.org>
To: Rob Herring <robh@...nel.org>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Stephen Boyd <sboyd@...nel.org>
Cc: Jeffrey Hugo <jhugo@...eaurora.org>,
Taniya Das <tdas@...eaurora.org>, jeffrey.l.hugo@...il.com,
linux-arm-msm@...r.kernel.org, harigovi@...eaurora.org,
devicetree@...r.kernel.org, mka@...omium.org,
kalyan_t@...eaurora.org, Mark Rutland <mark.rutland@....com>,
linux-clk@...r.kernel.org, hoegsberg@...omium.org,
Douglas Anderson <dianders@...omium.org>,
Michael Turquette <mturquette@...libre.com>,
linux-kernel@...r.kernel.org
Subject: [PATCH v4 06/15] clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocks
It's nicer to use ARRAY_SIZE instead of hardcoding. Had we always
been doing this it would have prevented a previous bug. See commit
74c31ff9c84a ("clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6").
Signed-off-by: Douglas Anderson <dianders@...omium.org>
---
Changes in v4: None
Changes in v3:
- Patch ("clk: qcom: Use ARRAY_SIZE in dispcc-sc7180...") split out for v3.
Changes in v2: None
drivers/clk/qcom/dispcc-sc7180.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index 397f5d9dafc8..dd7af41e47eb 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -154,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_4,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -168,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -188,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -201,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -215,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -229,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
@@ -244,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
@@ -267,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -280,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_5,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
@@ -295,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -309,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
- .num_parents = 1,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
--
2.25.0.341.g760bfbb309-goog
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