linux-kernel - Re: [PATCH] powerpc/32s: Slenderize

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Date:   Mon, 3 Feb 2020 18:16:47 +0100
From:   Christophe Leroy <christophe.leroy@....fr>
To:     Joakim Tjernlund <Joakim.Tjernlund@...inera.com>,
        "mpe@...erman.id.au" <mpe@...erman.id.au>,
        "paulus@...ba.org" <paulus@...ba.org>,
        "benh@...nel.crashing.org" <benh@...nel.crashing.org>
Cc:     "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] powerpc/32s: Slenderize _tlbia() for powerpc 603/603e



Le 03/02/2020 à 17:57, Joakim Tjernlund a écrit :
> On Mon, 2020-02-03 at 16:47 +0000, Christophe Leroy wrote:
>> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>>
>>
>> _tlbia() is a function used only on 603/603e core, ie on CPUs which
>> don't have a hash table.
>>
>> _tlbia() uses the tlbia macro which implements a loop of 1024 tlbie.
>>
>> On the 603/603e core, flushing the entire TLB requires no more than
>> 32 tlbie.
>>
>> Replace tlbia by a loop of 32 tlbie.
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@....fr>
>> ---
>>   arch/powerpc/mm/book3s32/hash_low.S | 13 ++++++++-----
>>   1 file changed, 8 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/book3s32/hash_low.S b/arch/powerpc/mm/book3s32/hash_low.S
>> index c11b0a005196..a5039ad10429 100644
>> --- a/arch/powerpc/mm/book3s32/hash_low.S
>> +++ b/arch/powerpc/mm/book3s32/hash_low.S
>> @@ -696,18 +696,21 @@ _GLOBAL(_tlbia)
>>          bne-    10b
>>          stwcx.  r8,0,r9
>>          bne-    10b
>> +#endif /* CONFIG_SMP */
>> +       li      r5, 32
>> +       lis     r4, KERNELBASE@h
>> +       mtctr   r5
>>          sync
>> -       tlbia
>> +0:     tlbie   r4
>> +       addi    r4, r4, 0x1000
> 
> Is page size always 4096 here or does it not matter ?

603 and its derivatives (G2, e300, ...) only support 4k pages.

And regardless, the reference manual says:

The tlbia instruction is not implemented on the MPC603e and when its 
opcode is encountered, an illegal instruction program exception is 
generated. To invalidate all entries of both TLBs, 32 tlbie instructions 
must be executed, incrementing the value in EA[15–19] by 1 each time

Christophe