linux-kernel - Re: [PATCH] microblaze: Prevent the overflow of the start

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Message-ID: <CAHTX3dJa09azvz=J4FbMAspt1x2wTaG3SWGWAzsDtOiEm7x5+Q@mail.gmail.com>
Date:   Tue, 4 Feb 2020 11:34:10 +0100
From:   Michal Simek <monstr@...str.eu>
To:     LKML <linux-kernel@...r.kernel.org>,
        Michal Simek <monstr@...str.eu>, git <git@...inx.com>
Cc:     Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>
Subject: Re: [PATCH] microblaze: Prevent the overflow of the start

út 14. 1. 2020 v 13:34 odesílatel Michal Simek <michal.simek@...inx.com> napsal:
>
> From: Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>
>
> In case the start + cache size is more than the max int the
> start overflows.
> Prevent the same.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>
> Signed-off-by: Michal Simek <michal.simek@...inx.com>
> ---
>
>  arch/microblaze/kernel/cpu/cache.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
> index 0bde47e4fa69..dcba53803fa5 100644
> --- a/arch/microblaze/kernel/cpu/cache.c
> +++ b/arch/microblaze/kernel/cpu/cache.c
> @@ -92,7 +92,8 @@ static inline void __disable_dcache_nomsr(void)
>  #define CACHE_LOOP_LIMITS(start, end, cache_line_length, cache_size)   \
>  do {                                                                   \
>         int align = ~(cache_line_length - 1);                           \
> -       end = min(start + cache_size, end);                             \
> +       if (start <  UINT_MAX - cache_size)                             \
> +               end = min(start + cache_size, end);                     \
>         start &= align;                                                 \
>  } while (0)
>
> --
> 2.24.0
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs