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Message-ID: <20200204043825.thpbqpz3ao7zqvlh@wunner.de>
Date: Tue, 4 Feb 2020 05:38:25 +0100
From: Lukas Wunner <lukas@...ner.de>
To: Alex Deucher <alexdeucher@...il.com>
Cc: Dave Airlie <airlied@...il.com>,
Lucas Stach <l.stach@...gutronix.de>,
Ben Skeggs <skeggsb@...il.com>,
Karol Herbst <karolherbst@...il.com>,
"Alex G." <mr.nuke.me@...il.com>,
Bjorn Helgaas <helgaas@...nel.org>,
Alexandru Gagniuc <alex_gagniuc@...lteam.com>,
Keith Busch <keith.busch@...el.com>, Jens Axboe <axboe@...com>,
Christoph Hellwig <hch@....de>,
Sagi Grimberg <sagi@...mberg.me>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Jan Vesely <jano.vesely@...il.com>,
Alex Williamson <alex.williamson@...hat.com>,
Austin Bolen <austin_bolen@...l.com>,
Shyam Iyer <Shyam_Iyer@...l.com>,
Sinan Kaya <okaya@...nel.org>,
Linux PCI <linux-pci@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: Issues with "PCI/LINK: Report degraded links via link bandwidth
notification"
On Mon, Feb 03, 2020 at 04:16:36PM -0500, Alex Deucher wrote:
> AMD has had a micro-controller on the GPU handling pcie link speeds
> and widths dynamically (in addition to GPU clocks and voltages) for
> about 12 years or so at this point to save power when the GPU is idle
> and improve performance when it's required. The micro-controller
> changes the link parameters dynamically based on load independent of
> the driver. The driver can tweak the heuristics, or even disable the
> dynamic changes, but by default it's enabled when the driver loads.
> The ucode for this micro-controller is loaded by the driver so you'll
> see fixed clocks and widths prior to the driver loading. We'd need
> some sort of opt out I suppose for periods when the driver has enabled
> dynamic pcie power management in the micro-controller.
Note that there are *two* bits in the Link Status Register:
* Link Autonomous Bandwidth Status
"This bit is Set by hardware to indicate that hardware has
autonomously changed Link speed or width, without the Port
transitioning through DL_Down status, for reasons other than to
attempt to correct unreliable Link operation. This bit must be set if
the Physical Layer reports a speed or width change was initiated by
the Downstream component that was indicated as an autonomous change."
* Link Bandwidth Management Status
"This bit is Set by hardware to indicate that either of the
following has occurred without the Port transitioning through
DL_Down status. [...] Hardware has changed Link speed or width to
attempt to correct unreliable Link operation, either through an
LTSSM timeout or a higher level process."
See PCIe Base Spec 4.0 sec 7.8.8, 7.8.7, 4.2.6.3.3.1.
The two bits generate *separate* interrupts. We only enable the
interrupt for the latter.
If AMD GPUs generate a Link Bandwidth Management Interrupt upon
autonomously changing bandwidth for power management reasons
(instead of to correct unreliability issues), that would be a
spec violation.
So the question is, do your GPUs violate the spec in this regard?
Thanks,
Lukas
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