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Message-ID: <1ja75x6xdd.fsf@starbuckisacylon.baylibre.com>
Date: Wed, 05 Feb 2020 13:18:22 +0100
From: Jerome Brunet <jbrunet@...libre.com>
To: Nicolas Belin <nbelin@...libre.com>, linus.walleij@...aro.org
Cc: Kevin Hilman <khilman@...libre.com>, linux-gpio@...r.kernel.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] pinctrl: meson-gxl: fix GPIOX sdio pins
On Wed 05 Feb 2020 at 12:22, Nicolas Belin <nbelin@...libre.com> wrote:
> In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused
> any issue so far because devices using these pins always take both pins
> so the resulting configuration is OK.
>
> Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
> Signed-off-by: Nicolas Belin <nbelin@...libre.com>
Reviewed-by: Jerome Brunet <jbrunet@...libre.com>
> ---
> drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
> b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
> index 72c5373c8dc1..e8d1f3050487 100644
> --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
> +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
> @@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
> static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
> static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
> static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
> -static const unsigned int sdio_cmd_pins[] = { GPIOX_4 };
> -static const unsigned int sdio_clk_pins[] = { GPIOX_5 };
> +static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
> +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
> static const unsigned int sdio_irq_pins[] = { GPIOX_7 };
>
> static const unsigned int nand_ce0_pins[] = { BOOT_8 };
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