linux-kernel - Re: [RFC PATCH v1 2/5] clk: tegra: Add Tegra210 CSI TPG clock gate

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Message-Id: <20200205192341.E4E482072B@mail.kernel.org>
Date:   Wed, 05 Feb 2020 11:23:41 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     frankc@...dia.com, hverkuil@...all.nl, jonathanh@...dia.com,
        skomatineni@...dia.com, thierry.reding@...il.com
Cc:     linux-media@...r.kernel.org, devicetree@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH v1 2/5] clk: tegra: Add Tegra210 CSI TPG clock gate

Quoting Sowjanya Komatineni (2020-01-28 10:23:18)
> Tegra210 CSI hardware internally uses PLLD for internal test pattern
> generator logic.
> 
> PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD
> out to CSI during TPG mode.
> 
> This patch adds this CSI TPG clock gate to Tegra210 clock driver
> to allow Tegra video driver to ungate CSI TPG clock during TPG mode
> and gate during non TPG mode.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
> ---

Acked-by: Stephen Boyd <sboyd@...nel.org>