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Message-ID: <1580969461-16981-2-git-send-email-yamonkar@cadence.com>
Date:   Thu, 6 Feb 2020 07:10:49 +0100
From:   Yuti Amonkar <yamonkar@...ence.com>
To:     <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <kishon@...com>, <robh+dt@...nel.org>, <mark.rutland@....com>,
        <maxime@...no.tech>
CC:     <jsarha@...com>, <tomi.valkeinen@...com>, <praneeth@...com>,
        <mparab@...ence.com>, <sjakhade@...ence.com>,
        <yamonkar@...ence.com>
Subject: [PATCH v4 01/13] dt-bindings: phy: Remove Cadence MHDP PHY dt binding

Remove the Cadence MHDP PHY bindings. The binding is added
in next commit in YAML format. It is renamed to adopt
torrent nomenclature.
This will not affect ABI as the driver has never been functional,
and therefore do not exist in any active use case.

Signed-off-by: Yuti Amonkar <yamonkar@...ence.com>
---
 .../bindings/phy/phy-cadence-dp.txt           | 30 -------------------
 1 file changed, 30 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
deleted file mode 100644
index 7f49fd54ebc1..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Cadence MHDP DisplayPort SD0801 PHY binding
-===========================================
-
-This binding describes the Cadence SD0801 PHY hardware included with
-the Cadence MHDP DisplayPort controller.
-
--------------------------------------------------------------------------------
-Required properties (controller (parent) node):
-- compatible	: Should be "cdns,dp-phy"
-- reg		: Defines the following sets of registers in the parent
-		  mhdp device:
-			- Offset of the DPTX PHY configuration registers
-			- Offset of the SD0801 PHY configuration registers
-- #phy-cells	: from the generic PHY bindings, must be 0.
-
-Optional properties:
-- num_lanes	: Number of DisplayPort lanes to use (1, 2 or 4)
-- max_bit_rate	: Maximum DisplayPort link bit rate to use, in Mbps (2160,
-		  2430, 2700, 3240, 4320, 5400 or 8100)
--------------------------------------------------------------------------------
-
-Example:
-	dp_phy: phy@...b030a00 {
-		compatible = "cdns,dp-phy";
-		reg = <0xf0 0xfb030a00 0x0 0x00000040>,
-		      <0xf0 0xfb500000 0x0 0x00100000>;
-		num_lanes = <4>;
-		max_bit_rate = <8100>;
-		#phy-cells = <0>;
-	};
-- 
2.20.1

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