lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <87v9ojg5r1.fsf@vitty.brq.redhat.com>
Date:   Thu, 06 Feb 2020 15:17:06 +0100
From:   Vitaly Kuznetsov <vkuznets@...hat.com>
To:     Paolo Bonzini <pbonzini@...hat.com>
Cc:     dgilbert@...hat.com, jmattson@...gle.com,
        linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Subject: Re: [PATCH] KVM: SVM: relax conditions for allowing MSR_IA32_SPEC_CTRL accesses

Paolo Bonzini <pbonzini@...hat.com> writes:

> Userspace that does not know about the AMD_IBRS bit might still
> allow the guest to protect itself with MSR_IA32_SPEC_CTRL using
> the Intel SPEC_CTRL bit.  However, svm.c disallows this and will
> cause a #GP in the guest when writing to the MSR.  Fix this by
> loosening the test and allowing the Intel CPUID bit, and in fact
> allow the AMD_STIBP bit as well since it allows writing to
> MSR_IA32_SPEC_CTRL too.
>
> Reported-by: Zhiyi Guo <zhguo@...hat.com>
> Analyzed-by: Dr. David Alan Gilbert <dgilbert@...hat.com>
> Analyzed-by: Laszlo Ersek <lersek@...hat.com>
> Signed-off-by: Paolo Bonzini <pbonzini@...hat.com>
> ---
>  arch/x86/kvm/svm.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index bf0556588ad0..a3e32d61d60c 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -4225,6 +4225,8 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  		break;
>  	case MSR_IA32_SPEC_CTRL:
>  		if (!msr_info->host_initiated &&
> +		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
> +		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
>  		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
>  		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
>  			return 1;
> @@ -4310,6 +4312,8 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
>  		break;
>  	case MSR_IA32_SPEC_CTRL:
>  		if (!msr->host_initiated &&
> +		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
> +		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
>  		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
>  		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
>  			return 1;

Reviewed-by: Vitaly Kuznetsov <vkuznets@...hat.com>

but out of pure curiosity, why do we need these checks?

At least for the 'set' case right below them we have:

        if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
                 return 1;

so if guest will try using unsupported features it will #GP. So
basically, these checks will only fire when reading/writing '0' and all
features are missing, right? Do we care?

-- 
Vitaly

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ