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Message-ID: <20200207044425.32398-2-vigneshr@ti.com>
Date: Fri, 7 Feb 2020 10:14:24 +0530
From: Vignesh Raghavendra <vigneshr@...com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Santosh Shilimkar <ssantosh@...nel.org>
CC: <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <t-kristo@...com>
Subject: [PATCH v2 1/2] dt-bindings: clock: Add binding documentation for TI syscon gate clock
Add dt bindings for TI syscon gate clock driver that is used to control
EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC.
Signed-off-by: Vignesh Raghavendra <vigneshr@...com>
---
.../bindings/clock/ti,am654-ehrpwm-tbclk.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
new file mode 100644
index 000000000000..98fcac2b41f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI syscon gate clock driver
+
+maintainers:
+ - Vignesh Raghavendra <vigneshr@...com>
+
+description: |
+
+ This binding uses common clock bindings
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+ compatible:
+ items:
+ - const: ti,am654-ehrpwm-tbclk
+
+ "#clock-cells":
+ const: 1
+
+ ti,tbclk-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the system controller node that has bits to
+ control eHRPWM's TBCLK
+
+required:
+ - compatible
+ - "#clock-cells"
+ - ti,tbclk-syscon
+
+examples:
+ - |
+ tbclk_ctrl: tbclk_ctrl@...0 {
+ compatible = "syscon";
+ reg = <0x4140 0x18>;
+ };
+
+ ehrpwm_tbclk: clk0 {
+ compatible = "ti,am654-ehrpwm-tbclk";
+ #clock-cells = <1>;
+ ti,tbclk-syscon = <&tbclk_ctrl>;
+ };
--
2.25.0
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