linux-kernel - Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

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Date:   Fri, 7 Feb 2020 14:35:40 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Kamal Dasu <kdasu.kdev@...il.com>, linux-mips@...r.kernel.org,
        bcm-kernel-feedback-list@...adcom.com
Cc:     Ralf Baechle <ralf@...ux-mips.org>,
        Paul Burton <paulburton@...nel.org>,
        James Hogan <jhogan@...nel.org>,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        Huacai Chen <chenhc@...ote.com>,
        Mike Rapoport <rppt@...ux.ibm.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines

On 2/7/20 2:33 PM, Kamal Dasu wrote:
> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
> line can contain two instruction cache lines (64B), or four data cache
> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
> secondary cache module (ZSCM) on DMA from device so that data returned is
> coherent during DMA read operations.
> 
> Signed-off-by: Kamal Dasu <kdasu.kdev@...il.com>

Reviewed-by: Florian Fainelli <f.fainelli@...il.com>

Thanks Kamal!
-- 
Florian