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Message-ID: <CAJsYDVLzwWfT24NGDJMJShwoG0Qrq06mLqamHbH0xedmMLdrAQ@mail.gmail.com>
Date: Tue, 11 Feb 2020 14:55:17 +0800
From: Chuanhong Guo <gch981213@...il.com>
To: Yingjoe Chen <yingjoe.chen@...iatek.com>
Cc: linux-mtd@...ts.infradead.org,
Vignesh Raghavendra <vigneshr@...com>,
Tudor Ambarus <tudor.ambarus@...rochip.com>,
Richard Weinberger <richard@....at>,
open list <linux-kernel@...r.kernel.org>,
linux-mediatek@...ts.infradead.org,
Miquel Raynal <miquel.raynal@...tlin.com>,
Matthias Brugger <matthias.bgg@...il.com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2] mtd: mtk-quadspi: add support for DMA reading
Hi!
On Mon, Feb 10, 2020 at 4:31 PM Yingjoe Chen <yingjoe.chen@...iatek.com> wrote:
> > DMA busy checking is implemented with readl_poll_timeout because
> > I don't have access to IRQ-related docs. The speed increment comes
> > from those saved cmd+addr+dummy clocks.
>
> Hi Chuanhong,
>
> Thanks for your patch, I'm checking with Guochun to see if we could
> release IRQ related information to you.
Thanks for the info.
I'd like to keep using polling mode in this patch for easier reviewing.
It's already a pretty lengthy patch now. I may implement IRQ support
in future patches.
>
> > This controller requires that DMA source/destination address and
> > reading length should be 16-byte aligned. We use a bounce buffer if
> > one of them is not aligned, read more than what we need, and copy
> > data from corresponding buffer offset.
>
> I've checked with our HW guys. The limitation is on DRAM only.
> So for read we should check buffer and length to make sure it is
> aligned, but don't need to check from.
My previous test on mt7629 shows that from address also needs to
be aligned. e.g. If I perform a DMA read from 0x2 I actually got data
starting from 0x0 instead.
Regards,
Chuanhong Guo
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