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Message-ID: <CAAhSdy0qK+MC4+Yu6OM20XwzrAennzyi68SOmkC5KAzPJOqTng@mail.gmail.com>
Date: Wed, 12 Feb 2020 10:27:08 +0530
From: Anup Patel <anup@...infault.org>
To: Atish Patra <atish.patra@....com>
Cc: "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
Albert Ou <aou@...s.berkeley.edu>,
Allison Randal <allison@...utok.net>,
Borislav Petkov <bp@...e.de>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
"Eric W. Biederman" <ebiederm@...ssion.com>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Heiko Carstens <heiko.carstens@...ibm.com>,
Jason Cooper <jason@...edaemon.net>,
Kees Cook <keescook@...omium.org>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Mao Han <han_mao@...ky.com>, Marc Zyngier <maz@...nel.org>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Michael Ellerman <mpe@...erman.id.au>,
Mike Rapoport <rppt@...ux.ibm.com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Thomas Gleixner <tglx@...utronix.de>,
Vincent Chen <vincent.chen@...ive.com>
Subject: Re: [PATCH v8 09/11] RISC-V: Add supported for ordered booting method
using HSM
On Wed, Feb 12, 2020 at 7:21 AM Atish Patra <atish.patra@....com> wrote:
>
> Currently, all harts have to jump Linux in RISC-V. This complicates the
> multi-stage boot process as every transient stage also has to ensure all
> harts enter to that stage and jump to Linux afterwards. It also obstructs
> a clean Kexec implementation.
>
> SBI HSM extension provides alternate solutions where only a single hart
> need to boot and enter Linux. The booting hart can bring up secondary
> harts one by one afterwards.
>
> Add SBI HSM based cpu_ops that implements an ordered booting method in
> RISC-V. This change is also backward compatible with older firmware not
> implementing HSM extension. If a latest kernel is used with older
> firmware, it will continue to use the default spinning booting method.
>
> Signed-off-by: Atish Patra <atish.patra@....com>
> ---
> arch/riscv/kernel/cpu_ops.c | 10 +++++++++-
> arch/riscv/kernel/cpu_ops_sbi.c | 31 +++++++++++++++++++++++++++++++
> arch/riscv/kernel/head.S | 26 ++++++++++++++++++++++++++
> arch/riscv/kernel/smpboot.c | 2 +-
> arch/riscv/kernel/traps.c | 2 +-
> 5 files changed, 68 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
> index 1085def3735a..6221bbedaea4 100644
> --- a/arch/riscv/kernel/cpu_ops.c
> +++ b/arch/riscv/kernel/cpu_ops.c
> @@ -18,6 +18,7 @@ const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
> void *__cpu_up_stack_pointer[NR_CPUS];
> void *__cpu_up_task_pointer[NR_CPUS];
>
> +extern const struct cpu_operations cpu_ops_sbi;
> extern const struct cpu_operations cpu_ops_spinwait;
>
> void cpu_update_secondary_bootdata(unsigned int cpuid,
> @@ -34,7 +35,14 @@ void cpu_update_secondary_bootdata(unsigned int cpuid,
>
> int __init cpu_set_ops(int cpuid)
> {
> - cpu_ops[cpuid] = &cpu_ops_spinwait;
> +#if IS_ENABLED(CONFIG_RISCV_SBI)
> + if (sbi_probe_extension(SBI_EXT_HSM) > 0) {
> + if (!cpuid)
> + pr_info("SBI v0.2 HSM extension detected\n");
> + cpu_ops[cpuid] = &cpu_ops_sbi;
> + } else
> +#endif
> + cpu_ops[cpuid] = &cpu_ops_spinwait;
>
> return 0;
> }
> diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c
> index 9bdb60e0a4df..31487a80c3b8 100644
> --- a/arch/riscv/kernel/cpu_ops_sbi.c
> +++ b/arch/riscv/kernel/cpu_ops_sbi.c
> @@ -7,9 +7,13 @@
>
> #include <linux/init.h>
> #include <linux/mm.h>
> +#include <asm/cpu_ops.h>
> #include <asm/sbi.h>
> #include <asm/smp.h>
>
> +extern char secondary_start_sbi[];
> +const struct cpu_operations cpu_ops_sbi;
> +
> static int sbi_hsm_hart_stop(void)
> {
> struct sbiret ret;
> @@ -46,3 +50,30 @@ static int sbi_hsm_hart_get_status(unsigned long hartid)
> else
> return ret.value;
> }
> +
> +static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
> +{
> + int rc;
> + unsigned long boot_addr = __pa_symbol(secondary_start_sbi);
> + int hartid = cpuid_to_hartid_map(cpuid);
> +
> + cpu_update_secondary_bootdata(cpuid, tidle);
> + rc = sbi_hsm_hart_start(hartid, boot_addr, 0);
> +
> + return rc;
> +}
> +
> +static int sbi_cpu_prepare(unsigned int cpuid)
> +{
> + if (!cpu_ops_sbi.cpu_start) {
> + pr_err("cpu start method not defined for CPU [%d]\n", cpuid);
> + return -ENODEV;
> + }
> + return 0;
> +}
> +
> +const struct cpu_operations cpu_ops_sbi = {
> + .name = "sbi",
> + .cpu_prepare = sbi_cpu_prepare,
> + .cpu_start = sbi_cpu_start,
> +};
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index c1be597d22a1..8386cfafba98 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -99,11 +99,37 @@ relocate:
> ret
> #endif /* CONFIG_MMU */
> #ifdef CONFIG_SMP
> + .global secondary_start_sbi
> +secondary_start_sbi:
> + /* Mask all interrupts */
> + csrw CSR_IE, zero
> + csrw CSR_IP, zero
> +
> + /* Load the global pointer */
> + .option push
> + .option norelax
> + la gp, __global_pointer$
> + .option pop
> +
> + /*
> + * Disable FPU to detect illegal usage of
> + * floating point in kernel space
> + */
> + li t0, SR_FS
> + csrc CSR_STATUS, t0
> +
> /* Set trap vector to spin forever to help debug */
> la a3, .Lsecondary_park
> csrw CSR_TVEC, a3
>
> slli a3, a0, LGREG
> + la a4, __cpu_up_stack_pointer
> + la a5, __cpu_up_task_pointer
> + add a4, a3, a4
> + add a5, a3, a5
> + REG_L sp, (a4)
> + REG_L tp, (a5)
> +
> .global secondary_start_common
> secondary_start_common:
>
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 2ee41c779a16..2c56ac70e64d 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -146,7 +146,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
> /*
> * C entry point for a secondary processor.
> */
> -asmlinkage __visible void __init smp_callin(void)
> +asmlinkage __visible void smp_callin(void)
> {
> struct mm_struct *mm = &init_mm;
>
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index f4cad5163bf2..0063dd7318d6 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -147,7 +147,7 @@ int is_valid_bugaddr(unsigned long pc)
> }
> #endif /* CONFIG_GENERIC_BUG */
>
> -void __init trap_init(void)
> +void trap_init(void)
> {
> /*
> * Set sup0 scratch register to 0, indicating to exception vector
> --
> 2.24.0
>
Overall, this patch looks good but SBI HSM helper functions
from PATCH8 should be moved to this patch.
Reviewed-by: Anup Patel <anup@...infault.org>
Regards,
Anup
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