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Date: Wed, 12 Feb 2020 13:17:56 +0100
From: Matthias Brugger <matthias.bgg@...il.com>
To: Ming-Fan Chen <ming-fan.chen@...iatek.com>,
Rob Herring <robh+dt@...nel.org>
Cc: Yong Wu <yong.wu@...iatek.com>, Evan Green <evgreen@...omium.org>,
Joerg Roedel <jroedel@...e.de>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, wsd_upstream@...iatek.com
Subject: Re: [PATCH v3 3/3] memory: mtk-smi: Add bandwidth initial golden
setting
On 08/01/2020 07:41, Ming-Fan Chen wrote:
> SMI bandwidth initial golden setting for MT6779 make sure
> better performance of memory control for multimedia modules.
>
> changelog since v2:
> Define local variable from long to short
> Merge writel_relaxed into one line
> Remove SMI_LARB_SW_FLAG in smi-larb
>
> Signed-off-by: Ming-Fan Chen <ming-fan.chen@...iatek.com>
> ---
> drivers/memory/mtk-smi.c | 118 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 117 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> index d0b747a..222ac7e 100644
> --- a/drivers/memory/mtk-smi.c
> +++ b/drivers/memory/mtk-smi.c
> @@ -41,21 +41,47 @@
> #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
> #define F_MMU_EN BIT(0)
>
> +#define SMI_LARB_CMD_THRT_CON 0x24
> +#define SMI_LARB_OSTDL_PORT 0x200
> +#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
> +
> /* SMI COMMON */
> +#define SMI_L1LEN 0x100
> +#define SMI_L1ARB0 0x104
> +#define SMI_L1ARB(id) (SMI_L1ARB0 + (((id) & 0x7) << 2))
> +
> #define SMI_BUS_SEL 0x220
> #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
> /* All are MMU0 defaultly. Only specialize mmu1 here. */
> #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
>
> +#define SMI_M4U_TH 0x234
> +#define SMI_FIFO_TH1 0x238
> +#define SMI_FIFO_TH2 0x23c
> +#define SMI_DCM 0x300
> +#define SMI_DUMMY 0x444
> +
> +#define SMI_LARB_PORT_NR_MAX 32
> +#define SMI_LARB_MISC_NR 1
> +
> enum mtk_smi_gen {
> MTK_SMI_GEN1,
> MTK_SMI_GEN2
> };
>
> +struct mtk_smi_reg_pair {
> + u16 offset;
> + u32 value;
> +};
> +
> struct mtk_smi_common_plat {
> enum mtk_smi_gen gen;
> bool has_gals;
> u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
> + bool has_bwc;
bwc = bandwith configuration ?
> + u8 larb_nr;
> + const u16 *l1arb;
> + const struct mtk_smi_reg_pair *misc;
maybe encapsulate this in a new struct mtk_smi_common_bwidth_config or something
like this?
> };
>
> struct mtk_smi_larb_gen {
> @@ -63,6 +89,9 @@ struct mtk_smi_larb_gen {
> void (*config_port)(struct device *);
> unsigned int larb_direct_to_common_mask;
> bool has_gals;
> + bool has_bwc;
> + const u8 (*ostdl)[SMI_LARB_PORT_NR_MAX];
array of pointers? maybe:
const u8 *ostdl[SMI_LARB_PORT_NR_MAX];
or even better
const u8 **ostdl;
> + const struct mtk_smi_reg_pair (*misc)[SMI_LARB_MISC_NR];
Same here.
> };
>
> struct mtk_smi {
> @@ -159,6 +188,8 @@ void mtk_smi_larb_put(struct device *larbdev)
> static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
> {
> struct mtk_smi_larb *larb = dev_get_drvdata(dev);
> + const struct mtk_smi_reg_pair *misc;
> + const u8 *ostdl;
> u32 reg;
> int i;
>
> @@ -170,6 +201,18 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
> reg |= F_MMU_EN;
> writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
> }
> +
> + if (!larb->larb_gen->has_bwc)
I'd prefer
if (larb->larb_gen->has_bwc) {
...
}
> + return;
> +
> + for (i = 0, ostdl = larb->larb_gen->ostdl[larb->larbid];
> + i < SMI_LARB_PORT_NR_MAX; i++)
ostdl = larb->larb_gen->ostdl[larb->larbid];
for (i = 0, ; i < SMI_LARB_PORT_NR_MAX; i++)
> + writel_relaxed(ostdl[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
> +
> + for (i = 0, misc = larb->larb_gen->misc[larb->larbid];
> + i < SMI_LARB_MISC_NR; i++)
same here.
> + writel_relaxed(misc[i].value, larb->base + misc[i].offset);
new line here.
> + wmb(); /* make sure settings are written */
> }
>
> static void mtk_smi_larb_config_port_mt8173(struct device *dev)
> @@ -239,11 +282,53 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
> .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
> };
>
> +static const u8 mtk_smi_larb_mt6779_ostdl[][SMI_LARB_PORT_NR_MAX] = {
static const u8 mtk_smi_larb_mt6779_ostdl[MTK_LARB_NR_MAX][SMI_LARB_PORT_NR_MAX]
otherwise if we forget a line, the driver could access random memory.
> + {0x28, 0x28, 0x01, 0x28, 0x01, 0x01, 0x0a, 0x0a, 0x28,},
> + {0x28, 0x01, 0x28, 0x28, 0x0a, 0x01, 0x01, 0x0d, 0x0d, 0x07,
> + 0x01, 0x07, 0x01, 0x28,},
> + {0x18, 0x01, 0x08, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
> + 0x01, 0x01},
> + {0x01, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01, 0x04, 0x02, 0x01,
> + 0x04, 0x01, 0x01, 0x01, 0x01, 0x04, 0x0b, 0x13, 0x14,},
> + {},
> + {0x13, 0x0f, 0x0d, 0x07, 0x07, 0x04, 0x03, 0x01, 0x03, 0x01,
> + 0x05, 0x0c, 0x01, 0x01, 0x08, 0x06, 0x02, 0x01, 0x08, 0x08,
> + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,},
> + {0x01, 0x01, 0x01,},
> + {0x01, 0x01, 0x01, 0x01,},
> + {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,},
> + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x04,
> + 0x04, 0x01, 0x01, 0x01, 0x02, 0x02, 0x04, 0x02, 0x01, 0x02,
> + 0x04, 0x02, 0x02, 0x01,},
> + {0x1f, 0x1a, 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x1f, 0x1a,
> + 0x02, 0x04, 0x1f, 0x02, 0x14, 0x01, 0x01, 0x02, 0x02, 0x04,
> + 0x02, 0x0a, 0x02, 0x02, 0x04, 0x02, 0x0a, 0x02, 0x04, 0x02, 0x04,},
> + {0x01, 0x01, 0x01, 0x01, 0x01,},
> +};
> +
> +static const struct mtk_smi_reg_pair
> +mtk_smi_larb_mt6779_misc[][SMI_LARB_MISC_NR] = {
same here.
> + {{SMI_LARB_CMD_THRT_CON, 0x370256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x300256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x370256},},
> + {},
> + {{SMI_LARB_CMD_THRT_CON, 0x300256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x300256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x300256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x300256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x370256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x370256},},
> + {{SMI_LARB_CMD_THRT_CON, 0x370256},},
> +};
> +
> static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
> .config_port = mtk_smi_larb_config_port_gen2_general,
> .larb_direct_to_common_mask =
> BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
> /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
> + .has_bwc = true,
> + .ostdl = mtk_smi_larb_mt6779_ostdl,
> + .misc = mtk_smi_larb_mt6779_misc,
> };
>
> static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
> @@ -397,11 +482,30 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
> .gen = MTK_SMI_GEN2,
> };
>
> +static const u16 mtk_smi_common_mt6779_l1arb[] = {
> + 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000, 0x1000,
> +};
> +
> +static const struct
> +mtk_smi_reg_pair mtk_smi_common_mt6779_misc[SMI_COMMON_MISC_NR] = {
> + {SMI_L1LEN, 0xb},
> + {SMI_M4U_TH, 0xe100e10},
> + {SMI_FIFO_TH1, 0x506090a},
> + {SMI_FIFO_TH2, 0x506090a},
> + {SMI_DCM, 0x4f1},
> + {SMI_DUMMY, 0x1},
> +};
> +
> static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
> .gen = MTK_SMI_GEN2,
> .has_gals = true,
> .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
> F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
> + .has_bwc = true,
> + .larb_nr = ARRAY_SIZE(mtk_smi_common_mt6779_l1arb),
> + .l1arb = mtk_smi_common_mt6779_l1arb,
> + .misc_nr = ARRAY_SIZE(mtk_smi_common_mt6779_misc),
> + .misc = mtk_smi_common_mt6779_misc,
> };
>
> static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
> @@ -506,7 +610,7 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev)
> {
> struct mtk_smi *common = dev_get_drvdata(dev);
> u32 bus_sel = common->plat->bus_sel;
> - int ret;
> + int i, ret;
>
> ret = mtk_smi_clk_enable(common);
> if (ret) {
> @@ -516,6 +620,18 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev)
>
> if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
> writel(bus_sel, common->base + SMI_BUS_SEL);
> +
> + if (!common->plat->has_bwc)
> + return 0;
> +
if (common->plat->has_bwc) {
...
}
return 0;
> + for (i = 0; i < common->plat->larb_nr; i++)
> + writel_relaxed(common->plat->l1arb[i],
> + common->base + SMI_L1ARB(i));
> +
> + for (i = 0; i < common->plat->misc_nr; i++)
> + writel_relaxed(common->plat->misc[i].value,
> + common->base + common->plat->misc[i].value);
> + wmb(); /* make sure settings are written */
> return 0;
> }
>
>
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