[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <085cdec7-1759-82c6-7a65-9b7d28c1c458@arm.com>
Date: Thu, 13 Feb 2020 07:45:55 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Gerald Schaefer <gerald.schaefer@...ibm.com>
Cc: Catalin Marinas <catalin.marinas@....com>, linux-mm@...ck.org,
Mark Rutland <mark.rutland@....com>,
linux-ia64@...r.kernel.org, linux-sh@...r.kernel.org,
Peter Zijlstra <peterz@...radead.org>,
James Hogan <jhogan@...nel.org>,
Tetsuo Handa <penguin-kernel@...ove.sakura.ne.jp>,
Heiko Carstens <heiko.carstens@...ibm.com>,
Michal Hocko <mhocko@...nel.org>,
Dave Hansen <dave.hansen@...el.com>,
Paul Mackerras <paulus@...ba.org>, sparclinux@...r.kernel.org,
Thomas Gleixner <tglx@...utronix.de>,
linux-s390@...r.kernel.org, Michael Ellerman <mpe@...erman.id.au>,
x86@...nel.org, Russell King - ARM Linux <linux@...linux.org.uk>,
Matthew Wilcox <willy@...radead.org>,
Steven Price <Steven.Price@....com>,
Jason Gunthorpe <jgg@...pe.ca>,
linux-snps-arc@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org,
Ingo Molnar <mingo@...nel.org>,
Kees Cook <keescook@...omium.org>,
Masahiro Yamada <yamada.masahiro@...ionext.com>,
Mark Brown <broonie@...nel.org>,
"Kirill A . Shutemov" <kirill@...temov.name>,
Dan Williams <dan.j.williams@...el.com>,
Vlastimil Babka <vbabka@...e.cz>,
Christophe Leroy <christophe.leroy@....fr>,
Sri Krishna chowdary <schowdary@...dia.com>,
Ard Biesheuvel <ard.biesheuvel@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-mips@...r.kernel.org, Ralf Baechle <ralf@...ux-mips.org>,
linux-kernel@...r.kernel.org, Paul Burton <paul.burton@...s.com>,
Mike Rapoport <rppt@...ux.vnet.ibm.com>,
Vineet Gupta <vgupta@...opsys.com>,
Martin Schwidefsky <schwidefsky@...ibm.com>,
Andrew Morton <akpm@...ux-foundation.org>,
linuxppc-dev@...ts.ozlabs.org,
"David S. Miller" <davem@...emloft.net>
Subject: Re: [PATCH V12] mm/debug: Add tests validating architecture page
table helpers
On 02/12/2020 11:25 PM, Gerald Schaefer wrote:
> On Wed, 12 Feb 2020 15:12:54 +0530
> Anshuman Khandual <anshuman.khandual@....com> wrote:
>
>>>> +/*
>>>> + * On s390 platform, the lower 12 bits are used to identify given page table
>>>> + * entry type and for other arch specific requirements. But these bits might
>>>> + * affect the ability to clear entries with pxx_clear(). So while loading up
>>>> + * the entries skip all lower 12 bits in order to accommodate s390 platform.
>>>> + * It does not have affect any other platform.
>>>> + */
>>>> +#define RANDOM_ORVALUE (0xfffffffffffff000UL)
>>>
>>> I'd suggest you generate this mask with something like
>>> GENMASK(BITS_PER_LONG, PAGE_SHIFT).
>>
>> IIRC the lower 12 bits constrains on s390 platform might not be really related
>> to it's PAGE_SHIFT which can be a variable, but instead just a constant number.
>> But can definitely use GENMASK or it's variants here.
>>
>> https://lkml.org/lkml/2019/9/5/862
>
> PAGE_SHIFT would be fine, it is 12 on s390. However, in order to be
> more precise, we do not really need all 12 bits, only the last 4 bits.
> So, something like this would work:
>
> #define RANDOM_ORVALUE GENMASK(BITS_PER_LONG - 1, 4)
>
> The text in the comment could then also be changed from 12 to 4, and
> be a bit more specific on the fact that the impact on pxx_clear()
> results from the dynamic page table folding logic on s390:
>
> /*
> * On s390 platform, the lower 4 bits are used to identify given page table
> * entry type. But these bits might affect the ability to clear entries with
> * pxx_clear() because of how dynamic page table folding works on s390. So
> * while loading up the entries do not change the lower 4 bits.
> * It does not have affect any other platform.
> */
Sure, will update accordingly.
Powered by blists - more mailing lists